Hi,
ADC3424 is designed in my product and found that some chips may have offset error which make the digital O/P too large and result a failure rate in production. My questions as below:
1. How to measure the offset error of ADC3424 with its EVK and TSW1400? I want to compare the offset error difference between passed chip and failed chip.
2. The full scale spec of ADC3424 is 2Vpp and offset error is +/-25mV, if my design only using 0.3Vpp I/P scale, would the offset error's effect get severe?
3. I couldn't find the linearity error such as Integral nonlinearity in datasheet, would you kindly provide it. Failed chips also showed some nonlinearity.
Thanks, Minchieh