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ADC3424: How to measure offset error of ADC3424 with its EVK and TSW1400?

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Part Number: ADC3424

Hi,

ADC3424 is designed in my product and found that some chips may have offset error which make the digital O/P too large and result a failure rate in production. My questions as below:

1. How to measure the offset error of ADC3424 with its EVK and TSW1400? I want to compare the offset error difference between passed chip and failed chip.

2. The full scale spec of ADC3424 is 2Vpp and offset error is +/-25mV, if my design only using 0.3Vpp I/P scale, would the offset error's effect get severe?

3. I couldn't find the linearity error such as Integral nonlinearity in datasheet, would you kindly provide it. Failed chips also showed some nonlinearity.

Thanks, Minchieh

  • Hi Minchieh,

    1. How to measure the offset error of ADC3424 with its EVK and TSW1400? I want to compare the offset error difference between passed chip and failed chip.

    It is probably better to test this with a DC level input on the EVK. Also, I want to make sure that you are aware that there is a chopper that moves the 1/f noise from DC (0 Hz) to FS/2. This is a useful feature for AC/Spectral applications, but may not be helpful when measuring DC levels. I would recommend disabling the chopper by writing address 0x522, data 0x02. Please see page 64 of the data sheet for more information on this register.

     

    2. The full scale spec of ADC3424 is 2Vpp and offset error is +/-25mV, if my design only using 0.3Vpp I/P scale, would the offset error's effect get severe?

    The offset error is a static parameter, so I do not think it should have a larger impact if the analog input is smaller than the full scale.

    3. I couldn't find the linearity error such as Integral nonlinearity in datasheet, would you kindly provide it. Failed chips also showed some nonlinearity.

    DNL is ~ +/- 0.1 LSB, and INL is ~ +/- 0.2 LSBs.

    Best Regards,

    Dan

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