ADS5407: Selectable interleaving correction - gain and offset

Hi Stefan,

There are no internal level shifters within the ADC if that is what you are asking.

In order to achieve fullscale of the ADC, the signal that you are applying must be level shifted outside of the converter at the analog inputs.

How this is done is typically by using an amplifier to create the level shift.

Something like the LMH5401 or the LMH32401 might be in line what you are trying to achieve.

Hope that helps.

Regards,

Rob

Hi Rob
I've got a level shifter outside ADC and it is based on LMH5401 and it works fine. Any changes in DAC are visible in the acquisition system.
After I've enabled correction in ADC, signals previously DC shifted are "moved" to DC 0V level and DAC has no effect on visible data.
My ADC config is like this:

0x2C   0b1101001011110000
0x00   0b1000000000000000
0x01   0b1000001000000010
0x03   0b0100101100011000
0x03   0b0000101100011000
0x1A   0b0100101100011000
0x1A   0b0000101100011000
0x3A   0b0000111000011000

Is ADC Interleaving correction is "transparent" to input DC level?

Regards,

Stefan

0878.adc_input.pdf

Hi Rob,

I thought the correction was done independently of the input circuit. In the previous post, there is a schematic of the input, and below you will find the waveforms from the oscilloscope and my acquisition system with and without correction.

Stefan

Hi Rob,

The common mode of LMH5401 (Pin2) is connected directly to ADS5407 pin B14 so it is 1.9V. R9 and R4 are to keep VCM at the input and the output of LMH5401 close to each other. This idea is based on "AN-2177 Using the LMH6554 as an ADC Driver". 

The input signal is mainly photomultiplier output (signal directly from anode) with 50Ohm to ground. Signal "is visible" by ADC and FPGA. FFT in FPGA shows large  noise peek at Fs/2=250Mhz. This might be because of disabled interleaving correction and is described in ADS5407 in "INTERLEAVING CORRECTION" section.

Regards,

Stefan

Hi Rob,

I've checked voltages with 50Ohm termination at the input. DAC output was set from -1.2V to 1.2V and voltage between R9 and R10 is from 1.76 V to 2.07 V

Regards,

Stefan

Hi Rob,

I've checked voltages with 50 Ohm termination at the input. DAC output was set that the input of U1 buffer is from -1.2V to 1.2V and voltage between R9 and R10 is from 1.76 V to 2.07 V

Regards,

Stefan

Hi Rob,

Thank you. I will definitely check it out. The measured voltage levels generally correspond to what I obtained in the simulation. 2.06V matches the case of a 1.2V DC level shift at the input. Maybe this layout is not suitable for my application? What it wants to achieve is a digital oscilloscope circuit with a programmable DC level shift. The input signal is always unipolar and the analog input circuits are to ensure the correct input voltage levels shift of the signal to ADC input voltage ranges. 

Regards,

Stefan

Hi Rob,

I've checked the simulation model (TINA file in attachmentadc_in.tsc) and DMM results. All measurements were performed with DAC level set to 0V and I've checked the voltage on R16 to be 0V using DMM. Two measurements were performed: 50Ohm termination at the input and with wave generator set to DC 1V  and 50 Ohm output. Measurements using DMM for 50Ohm are VIN 480mV  INP and INN 1.910V VOUTP and VOUTN 1.980V. Measurements using DMM for 1V DC and 50Ohm are: VIN 964mV  INP and INN 2.038V VOUTP 1.746V VOUTN 2.213V Those measurements are more or less equal with simulation results.

 Regards,

Stefan

Hi Stefan,

Can you forward me the schematic for the ADC portion as well please?

I would like to look there too.

Regards,

Rob

Hi Rob,

8078.adc.pdf Regards,

Stefan

Hi Rob,