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DAC5662A - Output latency

When looking at the AC timing, the parameter Tlat shows 4 clocks.  Does this mean that the DAC is pipelined and intended to have a continuous clock feed?  In other words, it is not intended for asynchronous writes.

Can someone please confirm or dispute this reading?

Thank you.

  • Lance

    The DAC is indeed pipelined to accomodate different input data modes and WRT to CLK handoff. So the latency is 4 clock cycles, which means at least 4 clock cycles have to be provided for the DATA to reach DAC output. You can still tie CLK and WRT together. Perhaps in your FPGA, you can use pipelined FF to generate these clock cycles and also program your comparator to accomodate for latency?

    Regards