Part Number: ADC08100EVM
I am having trouble finding information on the ADC08100EVM. I have the User's Guide, but this is missing some details.
First, it mentions the clock output (J2) but never specifies what this signal will look like. Will it be identical to the clock input with a delay?
Second, I would like to see a labelled schematic for the board. Specifically, I would like to see a table labeling each of the CMOS pins (J1). I do not have the TSW1400EVM and have no means of measuring the ADC output at this point. A similar question was raised here https://e2e.ti.com/support/data-converters/f/73/p/928986/3432060#3432060?jktype=e2e. The answer to that question attaches a link, but I am having trouble finding any such diagram there.
If you could point me in the right direction to get things started, I would really appreciate it! Thank you!
The clock outputs should be identical to the clock input with a delay.
Here is the folder containing the ADC08100EVM schematic: ADC08100EVM.zip
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In reply to David Chaparro:
Terrific, thank you!
One other thing: do you have any documentation on what the signal from each of the data out pins looks like? I am having trouble finding any mention of their voltage ranges in the manual.
In reply to Ian Schwartz:
The ADC08100 datasheet will have the voltage ranges for the data out pins. It will be in the electrical characteristics section of the datasheet.
So just to make sure I am understanding this correctly:
The only reason I ask is because the recommended voltage inputs for the evaluation board exceed the maximum ratings for that of the base chip and I want to be safe.
Yes, D0-D7 correspond to the EVM pins 9-23 and their voltages will be within the datasheet specs because the EVM sets Vd=3V, driver supply voltage, which the datasheet recommends.
The eval board takes the supply voltage 0-6V and uses an LDO to bring the voltage down to 3V for the ADC supplies.
Thank you for clearing that up for me.
Expanding on this question: when you say the LDO brings the voltage down for the ADC supplies, you are including the clock and analog input with that, right? I assume so since the user's manual mentions that we should use a 5dBm clock input, which would exceed the -0.3V lower limit mentioned in the ADC08100 data sheet.
A LDO is used to regulate an output voltage that is powered from a higher voltage source and is only used the on the supplies of the ADC. The clock and analog inputs are not controlled by the LDO.
The clock has a voltage range of -0.3V to 0.3+Va, Va is the supply voltage with max of 3.8V. This means that you want your clock to have a voltage somewhere between those two voltages. A 5dBm clock input is about 1.125Vpp and is within that range of voltages.
A standard AC clock signal of 1.125Vpp would go to -0.5625V, which is smaller than that lower limit of -0.3V. Are you saying I will need to include a DC offset?
Yes, you will need a DC offset so that the clock's amplitude is within the given range. If you take a look at the EVM schematic you can see how we are accomplishing this.
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