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ADS1118: Why DOUT/DRDY signal never go low after 32 bit transmission?

Tzyway Ooi
Prodigy 20 points
Part Number: ADS1118

Hi,

I am creating design to interact with ADS1118 devices. I am using 32 bits transmission and follow the same thing as shown in Figure 41 as shown in ADS1118 datasheet.

From the waveform shown in oscilloscope, the DOUT/DRDY never go low after the ADS1118 received data from the SPI master controller. This is contradict to Figure 41 in datasheet which stated that DOUT/DRDY need to go low after data is ready. My SPI master controller is designed to read the DOUT/DRDY after sending data to ADS1118 and check if DOUT/DRDY goes low.

Checking on the timing parameter, the spi clock is running at 1MHz which is complied to the max 4Mhz stated in datasheet. Beside, the CSn signal asserted until the first rising edge of SPI clock has been more than 100ns which is also complied to the spec.

I am using Single Shot mode. The read back on Config MSB and Config LSB seems to be correct. Wonder if why DOUT/DRDY(MISO) never goes low?

Details of signal:

Blue -> SCLK, Purple - CSn, Yellow -> MOSI, Green -> MISO

  • 0
    TI__Guru* 92655 points

    Tzyway,


    Looking at the waveform, it generally looks correct. The value you are sending to the configuration register is C182h which is this setting:

    Start a single conversion (when in power-down state)
    AINP = AIN0 and AINN = GND
    FSR = ±6.144 V
    Single-shot mode or power-down state (default)
    128 SPS (default)
    ADC mode (default)
    Pullup resistor disabled on DOUT/DRDY pin
    Valid data; update the Config register (default)
    Always reads back 1

    The last two bytes on DOUT looks like it reads back 4183h, which I think is also a correct value because of the read back on bits 15 and 0. There is also data being read back as you can see on the first two bytes of DOUT, which may come from the previous conversion of the ADC.

    Because you have the device set to 128SPS, the nominal data rate is 7.81ms. When you look at DOUT, the read of the last bit forces DOUT high. If the device starts a conversion here, then DOUT will not go low until the conversion completes and you will need to wait 7.81ms (and then add 10% for oscillator variation and may be 20us to start up the device to make it about 8.62ms) to have the conversion complete.

    If the ADC is in the process of making an ADC conversion, the new configuration does start a new conversion immediately. The device completes the conversion in progress before starting a new conversion. If you are not getting the DOUT to go low, I would keep /CS low and wait at least 8.62ms to see when the conversion completes.

    It looks like you tried to add a second waveform, but it didn't get added to your last post. I'm not sure what that image was supposed to show. If you can, add it to your reply with the picture icon (do not use copy/paste).

    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 20 points

    Hi Joseph,

    Thanks for the details. The above mentioned config value (4183h)  did having MISO goes low. I did not notice that i am sending 058Bh in the next SPI transaction and hence another new conversion is not triggered. My spi master is polling for MISO goes low after the 058Bh spi transaction. It was my mistake.

    Would like to check with you if we are not triggering conversion, MISO line will always stay high?

  • 0 in reply to Tzyway Ooi
    TI__Guru* 92655 points

    Tzyway, 

    If the 32-bit data transmission is used and the conversion is not triggered, then the DOUT will remain high. There isn't anything in the device's state machine to return it low. DOUT would only return low as an indication that the conversion is complete.

    Joseph Wu