Part Number: ADC32RF45
I am using ADC32RF45 at bypass mode at 12 bit 3GHz. My sysref frequency is continous with frequency something like 2.3...MHz. When I digitize a radar pulse modulated at 2250MHz, 2625MHz and 1875MHz I get the disturbed pulse envelopes given below. A normal pulse at any other frequency is something like given below with the name "no_error". What is the reason for these disturbed pulses at these specific frequencies? Do you think it may be something related to offset correction, because it is disabled in my design. Any help is greatly appreciated.
Pulse is modulated at 1875MHz
Pulse is modulated at 2250MHz
Pulse is modulated at 2625MHz
If offset corrector is not disabled, tones at n*Fs/4 will be nulled. As we are not seeing that, offset corrector is disabled and it can't be the reason for this behavior.
I'm checking with the design team about this issue. I will get back to you with a response by Wednesday.
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In reply to Vijayendra Varma Siddamsetty:
One other thing is that we use a custom FMC board that we designed using ADC32RF45 module. We are not using EVM or anything like that.
In reply to E G:
Apart from the offset correction, ADC32RF45 has an interleaving corrector (IL corrector) that works in the background. This block estimates and compensates for mismatches among interleaving cores to suppress interleaving spurs (at fS / 2 – fIN and fS / 4 ± fIN)
We suspect that this background correction loop is causing the issue that you see with n*Fs/4 pulsed tone inputs. Can you please do below experiment to confirm:
1. After reset and ADC bringup, input a non n*Fs/4 tone to an ADC channel.
2. Freeze IL corrector for that channel (using below writes)
3. Input an n*Fs/4 pulsed tone to that channel and verify if the issue is resolved.
Freeze IL corrector – CHA:
0x4004 0x68 // Upper byte of page address 0x68000000
0x60FD 0x02 // Setting bit D1 freezes IL engine for CH-A (Note: bit D3 of the same register is meant for freezing CH-B)
Freeze IL corrector – CHB:
0x60FD 0x08 // Setting bit D3 freezes IL engine for CH-B (Note: bit D1 of the same register is meant for freezing CH-A)
Unfreeze IL corrector – CHA:
0x60FD 0x00 // Clearing bit D1 unfreezes IL engine for CH-A (Note: bit D3 of the same register is meant for (un)freezing CH-B)
Unfreeze IL corrector – CHB:
0x60FD 0x00 // Clearing bit D3 freezes IL engine for CH-B (Note: bit D1 of the same register is meant for (un)freezing CH-A)
I'll try it ASAP and let you know the result.
Do you want me apply the above steps after all of the ADC registers are configured, including ILConfig_Nyq2 and NLConfigNyq2 registers?
By the way can you please send me a link for the latest register settings for IL and NL for 3GSPs bypass mode?
Yes. Please follow above steps after ADC configuration as you were doing previously (this is what I meant by 'bringup' in step 1).
Input a pulsed tone at frequency other than n*Fs/8 and verify output is expected then freeze IL corrector and input a pulsed tone at n*Fs/8.
ADC32RF45 NL and IL register configuration can be found at below link:
Let me summarize what I did:
I programmed ADC and then input a pulse modulated tone at 2400MHz and observed that it got sampled without any problem,
While the signal generator is still on I did a freeze on IL corrector and then set the signal generator to give a pulse modulated tone at 2250MHz
and unfortunately I observed that the same problem still persists. I assumed that when I program the ADC as you suggested, IL corrector goes on automatically. Correct me if I am wrong. I mean I didn't do any unfreeze or anything like that at the very beginning right after ADC was brought up.
I appreciate your effort to resolve the issue, any other idea is appreciated.
Yes. You tested it as I wanted. Thanks. I was not sure if it would help.
I will check with the design team and get back to you latest by Tuesday.
I tested ADC32RF45EVM with a pulsed tone (at n*Fs/8 frequency) input and don't see this issue. From the amplitude vs time plot you sent, ADC output tone power reduced by ~20dB just after input is nulled. So output digital codes peak to peak should reduce to 0.1 times (of that of value with tone) immediately and then die down to noise floor in about 0.03s. But I'm not seeing this on ADC32RF45EVM.
Can you send a time domain plot of the Rx output?
I'll work on the time domain plot and send you a copy. Meanwhile when I left the offset corrector on by setting the appropriate reg value to x"22" as opposed to x"42"(datasheet is probably wrong) I expect the adc to null the single tones at nFs/8, correct me if I am wrong. I input a single tone(CW) at 2250 and I still see the tone at the output of the ADC(offset corrector is on). I am just bringing this up to see if I am doing anything wrong with the programming of the registers. But still, pulsed tones at other frequencies work just fine..
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