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ADC32RF45: adc32rf45

Part Number: ADC32RF45
Other Parts Discussed in Thread: , LMK04828

Hi,

I am using ADC32RF45 at bypass mode at 12 bit 3GHz. My sysref frequency is continous with frequency something like 2.3...MHz. When I digitize a radar pulse modulated at 2250MHz, 2625MHz and 1875MHz I get the disturbed pulse envelopes given below. A normal pulse at any other frequency is something like given below with the name "no_error". What is the reason for these disturbed pulses at these specific frequencies? Do you think it may be something related to offset correction, because it is disabled in my design. Any help is greatly appreciated. 

Pulse is modulated at 1875MHz

Pulse is modulated at 2250MHz

Pulse is modulated at 2625MHz

no_error

  • HI EG,

    If offset corrector is not disabled, tones at n*Fs/4 will be nulled. As we are not seeing that, offset corrector is disabled and it can't be the reason for this behavior. 

    I'm checking with the design team about this issue. I will get back to you with a response by Wednesday.

    Regards,

    Vijay

  • One other thing is that we use a custom FMC board that we designed using ADC32RF45 module. We are not using EVM or anything like that. 

  • Hi EG,

    Apart from the offset correction, ADC32RF45 has an interleaving corrector (IL corrector) that works in the background. This block estimates and compensates for mismatches among interleaving cores to suppress interleaving spurs (at fS / 2 – fIN and fS / 4 ± fIN)

    We suspect that this background correction loop is causing the issue that you see with n*Fs/4 pulsed tone inputs. Can you please do below experiment to confirm:

    1. After reset and ADC bringup, input a non n*Fs/4 tone to an ADC channel.

    2. Freeze IL corrector for that channel (using below writes)

    3. Input an n*Fs/4 pulsed tone to that channel and verify if the issue is resolved. 

    Freeze IL corrector – CHA:

    0x4004 0x68 // Upper byte of page address 0x68000000

    0x4003 0x00

    0x4002 0x00

    0x4001 0x00

    0x60FD 0x02 // Setting bit D1 freezes IL engine for CH-A (Note: bit D3 of the same register is meant for freezing CH-B)

    Freeze IL corrector – CHB:

    0x4004 0x68 // Upper byte of page address 0x68000000

    0x4003 0x00

    0x4002 0x00

    0x4001 0x00

    0x60FD 0x08 // Setting bit D3 freezes IL engine for CH-B (Note: bit D1 of the same register is meant for freezing CH-A)

    Unfreeze IL corrector – CHA:

    0x4004 0x68 // Upper byte of page address 0x68000000

    0x4003 0x00

    0x4002 0x00

    0x4001 0x00

    0x60FD 0x00 // Clearing bit D1 unfreezes IL engine for CH-A (Note: bit D3 of the same register is meant for (un)freezing CH-B)

    Unfreeze IL corrector – CHB:

    0x4004 0x68 // Upper byte of page address 0x68000000

    0x4003 0x00

    0x4002 0x00

    0x4001 0x00

    0x60FD 0x00 // Clearing bit D3 freezes IL engine for CH-B (Note: bit D1 of the same register is meant for (un)freezing CH-A)

    Regards,

    Vijay

  • I'll try it ASAP and let you know the result.

  • Hi,

    Do you want me apply the above steps after all of the ADC registers are configured, including ILConfig_Nyq2 and NLConfigNyq2 registers?

    By the way can you please send me a link for the latest register settings for IL and NL for 3GSPs bypass mode?

    Regards

  • Hi EG,

    Yes. Please follow above steps after ADC configuration as you were doing previously (this is what I meant by 'bringup' in step 1).

    Input a pulsed tone at frequency other than n*Fs/8 and verify output is expected then freeze IL corrector and input a pulsed tone at n*Fs/8.

    ADC32RF45 NL and IL register configuration can be found at below link:

    Regards,

    Vijay

  • Hi Vijay,

    Let me summarize what I did:

    I programmed ADC and then input a pulse modulated tone at 2400MHz and observed that it got sampled without any problem,

    While the signal generator is still on I did a freeze on IL corrector  and then set the signal generator to give a pulse modulated tone at 2250MHz 

    and unfortunately I observed that the same problem still persists. I assumed that when I program the ADC as you suggested, IL corrector goes on automatically. Correct me if I am wrong. I mean I didn't do any unfreeze or anything like that at the very beginning right after ADC was brought up.

    I appreciate your effort to resolve the issue, any other idea is appreciated.

    Regards

  • Hi EG,

    Yes. You tested it as I wanted. Thanks. I was not sure if it would help.

    I will check with the design team and get back to you latest by Tuesday. 

    Regards,

    Vijay

  • Hi EG,

    I tested ADC32RF45EVM with a pulsed tone (at n*Fs/8 frequency) input and don't see this issue. From the amplitude vs time plot you sent, ADC output tone power reduced by ~20dB just after input is nulled. So output digital codes peak to peak should reduce to 0.1 times (of that of value with tone) immediately and then die down to noise floor in about 0.03s. But I'm not seeing this on ADC32RF45EVM.

    Can you send a time domain plot of the Rx output?

    Regards,

    Vijay

  • Hi Vijay,

    I'll work on the time domain plot and send you a copy. Meanwhile when I left the offset corrector on by setting the appropriate reg value to x"22" as opposed to x"42"(datasheet is probably wrong) I expect the adc to null the single tones at nFs/8, correct me if I am wrong. I input a single tone(CW) at 2250 and I still see the tone at the output of the ADC(offset corrector is on). I am just bringing this up to see if I am doing anything wrong with the programming of the registers. But still, pulsed tones at other frequencies work just fine..

    Regards

  • Hi Vijay,

    I am sending you the results for 1875MHz, ADC exhibit the same behavior at the other 2 frequencies(2250MHZ and 2625MHz ). Below you can find the time domain plot(at different zooms) and spectrogram of the pulse modulated tone at 1875MHz. y axis is the value of the pure digital value that is read off of the ADC. How we do this analysis is as follows. We first record the digitized data and then open it using a matlab program that we developed.

  • Hi Vijay,

    Can you please also send me your register settings that you used for the EVM board? I'd like to compare it with mine.

    Regards

  • Hi EG,

    Offset corrector block should null inputs at n*Fs/8 when the offset corrector page register 0x6068 is set to 0x22 (There is an error in DS Table 118).

    If you are not seeing this, something might be wrong with the configuration.

    I was using EVM GUI to program ADC. I will find the config file GUI is using and send you tomorrow. 

    Regards,

    Vijay

  • Hi EG,

    ADC config file:

    DDC_bypass_82820_full_Ny2.cfg

    When you run this, offset corrector should be enabled. n*Fs/8 input tones will be nulled. Please verify this on your board. Then you can disable offset corrector and check if the issue persists. 

    Regards,

    Vijay

  • Hi Vijay,

    When I looked at your register settings I noticed 3 main differences(I am going to to check in more detail later). 

    1) I don't toggle sysref through SPI. It comes out of LMK04828 continously and ADC is fed with sysref before it got programmed.

    2) To enable offset corrector you set register 0x6068 to 0x42. Is it not supposed to be set to 0x22?

    3) I power down channel B since I dont use it. Thus, I dont do NL_config_Nyqx_chb. is it a problem?

    Regards

  • Hi EG,

    1. If continuous sysref is enabled during programming, it should be to okay not to toggle sysref through SPI. Just to make sure two sysref pulses are given at this point before programming is continued, this can be added.  

    2. Programming register to 0x42 also enables offset corrector. This can be changed to 0x22 for uniformity. 

    3. At the end of NL_config_Nyqx_chb, there are some register writes common for both channels. So this also should be included in full config. 

    Regards,

    Vijay

  • Hi Vijay,

    First of all I'd like to thank you for all the effort that you put out to resolve the issue. I really appreciate that. The issue is finally resolved. It was all because of unfrozen offset corrector. What I did initially was setting the offset corrector right after Powerup_Analog_Config programming stage and then wait about 50ms and then freeze the coefficients and continue with IL_Config_Nyqx_chA programming stage. This simply did not work. When I tried to freeze the offset corrector after all of the registers are programmed then everything worked out just fine. Thanks again..

    Regards