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ADC08D1020: Interleaving ADC1 & ADC2 channel with Extended mode

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Replies: 19

Views: 113

Part Number: ADC08D1020

Hello,

We want to interleave ADC1 & ADC2 in DES either from input I or Q to operate the ADC08D1020 at 2GS/s.

We use the Extended mode to have access to the 9 configuration registers. We intend to do the interleaving calibration with our own algorithm.

We notice:

  1. when input Q is selected, varying the Q offset not only changes ADC2 offset but also ADC1 offset. Could you please confirm it is correct? (we would have expected only ADC2 to change)
  2. According to the datasheet table 4, varying the Sampling Clock Phase Adjust does equally change ADC1 & ADC2 phases. Could you please confirm it is correct? (with the block diagram below, one could think that the relative phase between ADC1 & ADC2 can be changed)

Based on the two points above, it looks like it is not possible to do our own interleaving calibration and that we have to use the internal calibration. Could you please confirm it is correct?

Regards,

Nicolas

  • Hi Nicolas,

    I will need to address this with design and confirm.

    I will get back to you.

    Regards,

    Rob

     Rob Reeder

    Application Engineer

    High Speed Converter Group

    Texas Instruments Inc.

  • In reply to Rob Reeder:

    Hi Nicolas,

    I apologize, I am still waiting to hear back from design for a confirmation on this.

    It is not clear to me either on the EVM setup or datasheet if the two ADC channels are separate controls for offset and timing adjust in DES mode.

    Regards,

    Rob

     Rob Reeder

    Application Engineer

    High Speed Converter Group

    Texas Instruments Inc.

  • In reply to Rob Reeder:

    Hi Nicolas,

    You can adjust the offset and gain per each ADC channel independently. I did verify this on the EVM setup.

    However, you cannot adjust the clock phase adjust on each ADC channel independently unfortunately. I verified this as well and from design.

    If you require the independent clock phase adjust, then the ADC12DL3200 would be the next best choice for this.

    Regards,

    Rob

     Rob Reeder

    Application Engineer

    High Speed Converter Group

    Texas Instruments Inc.

  • In reply to Rob Reeder:

    Bonjour,

    Are the test you did with the EVM in DES mode? According to what follows, we are unable to have two independent offset and gain control in DES mode!

    Here are the two files containing the resulting of a 2D sweep of the offset and fullscale on input I.
    Values for offset and fullscale of channel Q are left to zero.
    One file is with the ADC configured using DES, the second without.
    The value I and value Q in the files are the average of 60'000 ADC output samples (30'000 each).
    The inputs of the ADC are connected to a constant voltage.

    We can see that in Non-DES mode (on the left), the ADC I has its output value changing according to the offset and fullscale values written to the channel I registers, whereas the output value of ADC Q does not change, according to the constant offset and fullscale values written to channel Q registers.

    On the other hand, in DES mode (on the right), the output of both ADC I and ADC Q are changing according to offset and fullscale values written to the channel I register of the ADC, even if the values written to offset and fullscale registers of channel Q are kept constant to zero.

    Non-DES registers
    0x00007fff Calibration Register
    0x0000b1ff Configuration Register
    0x0000007f Channel I Offset
    0x0000807f Channel I Full Scale
    0x0000007f Channel Q Offset
    0x0000807f Channel Q Full Scale
    0x000003ff Extended Configuration
    0x0000007f Phase Coarse Adjust
    0x000000ff Phase Fine Adjust

    DES registers
    0x00007fff Calibration Register
    0x0000b1ff Configuration Register
    0x0000007f Channel I Offset
    0x0000807f Channel I Full Scale
    0x0000007f Channel Q Offset
    0x0000807f Channel Q Full Scale
    0x000023ff Extended Configuration
    0x0000007f Phase Coarse Adjust
    0x000000ff Phase Fine Adjust

    (In bold, the registers that are changing their value during the 2D sweep.)

    AD08D1020.txtAD08D1020-DES.txt

  • In reply to Nicolas Schlumpf:

    Hi Nicolas,

    I believe I left out that detail. Sorry about that....

    First, you need to config the offset and gain in nonDes mode, then apply Des mode to the device continue to see the offset and gain changes.

    Regards,

    Rob

     Rob Reeder

    Application Engineer

    High Speed Converter Group

    Texas Instruments Inc.

  • In reply to Rob Reeder:

    Bonjour,

    I tried the following sequence between each step of the sweep, and the result is still the same. Both output values of ADC I and ADC Q follow the output and fullscale values of channel I registers.

    DES registers
    0x000003ff Extended Configuration -> Reset DES mode bit
    0x0000007f Channel I Offset
    0x0000807f Channel I Full Scale
    0x0000007f Channel Q Offset
    0x0000807f Channel Q Full Scale
    0x000023ff Extended Configuration -> Set DES mode bit
    0x0000007f Phase Coarse Adjust
    0x000000ff Phase Fine Adjust

    So, no. It does not solve the issue.

    Best regard
    Didier

  • In reply to Didier Trosset:

    Hi Didier,

    Here is what I am suggesting....

    Non-DES registers
    0x00007fff Calibration Register
    0x0000b1ff Configuration Register
    0x0000007f Channel I Offset
    0x0000807f Channel I Full Scale
    0x0000007f Channel Q Offset
    0x0000807f Channel Q Full Scale
    0x000003ff Extended Configuration
    0x0000007f Phase Coarse Adjust
    0x000000ff Phase Fine Adjust

    Then, put into DES mode.

    Then, acquire the analog signal.

    Regards,

    Rob

     Rob Reeder

    Application Engineer

    High Speed Converter Group

    Texas Instruments Inc.

  • In reply to Rob Reeder:

    Bonjour Rob,

    Here's what I tried in my 2D sweep loop.
    Note that I had to add the Resistor Trim Disable bit so that the DCLK do not stop when writing the configuration register.

    0x00007fff; Set Calibration
    0x000043ff; Set Extended Configuration -> Set the Resistor Trim Disable bit (DCLK must not stop)
    0x0000b1ff; Set Configuration Register
    0x0000c07f; Set Channel I Offset
    0x0000407f; Set Channel I Full Scale
    0x0000007f; Set Channel Q Offset
    0x0000807f; Set Channel Q Full Scale
    0x000043ff; Set Extended Configuration -> Non-DES mode
    0x0000007f; Set Phase Coarse Adjust
    0x000000ff; Set Phase Fine Adjust
    0x000063ff; Set Extended Configuration -> DES mode

    Result still the same.

    Could it really help to write first the offset and fullscale registers to the default value, and then to the value I want?

    Best regards
    DIdier

  • In reply to Didier Trosset:

    Hi Didier,

    Please try this sequence.....and let me know if you see any changes in DES mode.

    this is what I do on the WaveVision5 Software and I can see changes to both I and Q channels, then I put it in DES mode.

    0x00007fff; Set Calibration
    0x000003ff; Set Extended Configuration
    0x0000c07f; Set Channel I Offset
    0x0000407f; Set Channel I Full Scale
    0x000023ff; Set Extended Configuration -> DES mode

    Thanks,

    Rob

     Rob Reeder

    Application Engineer

    High Speed Converter Group

    Texas Instruments Inc.

  • In reply to Rob Reeder:

    Bonjour Rob,

    I'm sorry but I guess I have not explained clearly my issue.

    Indeed, you wrote: "I can see changes to both I and Q channels". That's my problem! When I write to the channel I register, I would like to see the changes applied only to the samples coming out of the ADC I. Even in DES mode. And it's not what I'm experiencing.

    Trying to get a better mutual understanding, we prepared two diagrams describing the internal layout of the ADC08D1020. In each of them, there are:

    • two inputs, I and Q,
    • two ADC, I and Q,
    • a Crosspoint Switch (CPS), routing the inputs to the ADC depending on DES mode and I/Q selection*, and
    • the I and Q adjustable gain/offset controls.

    They differ in the position of the I and Q adjustable gain/offset controls: they can be placed before the CPS, or after the CPS.

    Gain/Offset Controls BEFORE the CPS.

    Gain/Offset Controls AFTER the CPS.

    Could you tell us which of these two layouts best describes the internals of the ADC08D1020?

    Best regards
    Didier

    *: CPS logic depends Extended Configuration register bits 12 (Input Selector I or Q) and 13 (DES Enable).

    Mode Routing
    Non-DES Input I --> ADC I
    Input Q --> ADC Q
    DES input I

    Input I --> ADC I & ADC Q
    Input Q --> void

    DES input Q

    Input I --> void
    Input Q --> ADC I & ADC Q