ADS131M08: Irrelevant response received from ADC.

Hi Prasad,

Thank you for your post and welcome to our forum!

It looks like the STATUS register contents are reading back as 0x02FF, which would indicate that you expect the data to be zero-padded. Is that how you've programmed the MODE register? Please provide the register map settings, preferably in a separate text file.

You may have an issue with SPI frames overlapping /DRDY interrupts in your routine. I say that because the last byte of all your data samples begins with the same 0x02, just like the first byte in the STATUS word. That's just a guess - can you check the timing of your SPI transactions and ensure they are completed between /DRDY interrupts?

Best regards,

Hi Ryan,
1)

Received response in hex format -> 02FF8079834E867D41794FFCBFFFFFFFFCA37FFE66F9662FF9498F515000

Received response converted in binary format ->0000 0010 1111 1111 1000 0000 0111 1001 1000 0011 0100 1110 1000 0110 0111 1101 0100 0001 0111 1001 0100 1111 1111 1100 1011 1111 1111 1111 1111 1111 1111 1111 1111 1100 1010 0011 0111 1111 1111 1110 0110 0110 1111 1001 0110 0110 0010 1111 1111 1001 0100 1001 1000 1111 0101 0001 0101 0000 0000 0000

Received response left shifted by 1 bit -> 0000 0101 1111 1111 0000 0000 1111 0011 00000 1101 0011 1010 0001 1001 1111 0101 0000 0101 1110 010 1001 1111 1111 1001 0111 1111 1111 1111 1111 1111 1111 1111 1111 1001 0100 0110 1111 1111 1111 1100 1100 1101 1111 0010 1100 1100 0101 1111 1111 0010 1001 0011 0001 1110 1010 0010 1010 0000 0000 0000
Received response in hex format after left shifting by 1 bit -> 05FF00F3069D0CFA82F29FF97FFFFFFFF946FFFCCDF2CC5FF2931EA2A000

if we calculate crc for 05FF00F3069D0CFA82F29FF97FFFFFFFF946FFFCCDF2CC5FF2931EA2 we get A000.
so the received response is correct but we need left shift by 1.
why this is so?

2)The first two bytes we received after reset are 7F 94 if we perform left shift by 1 bit we get FF 28 which is correct.

3)We are providing 8 MHz SMCLK (Pin no. 67 of MSP430FR59941) to the CLKIN of ADC.Is it okay?

4)If we do not provide clock to clkin pin all the bytes received between 02FF and CRC are zero.I think the clkin is required for ADC sampling only and we still communicate with ADC through SPI.Can we read registers or write to the registers of ADC without providing clkin?

5)If we try to use WREG command we get the same response mentioned above which is for null command.(1 word of command(1 byte of zero padding),1 word of CRC(all zeroes),8 words of zeroes, 1 word= 3 bytes,1 frame=10 words)

6)Does all commands require minimum 10 words to complete the frame.

7)Does CLKIN and SCLK of SPI need to be synchronized for proper communication? What I understand from datasheet is synchronization only improves SNR.

Hi Ryan,

1.I came to a conclusion that ADC is not receiving command properly on the basis of following points:

a) Because there is problem with receiving MSB bit  there may be problem with MSB while transmitting also.

b) For every command sent I receive the response for null command and as per datasheet if ADC is unable to understand the command it assumes it as a null.

2) So I tried to send command by shifting to right by 1 bit(instead of A0 00 00 we sent 50 00 00 for reading ID register) and if we shift the received response by 1 bit we get the expected response. Please review the below table.

3) After doing above task I did following changes in program :

    i) I configured SPI in mode 1 before making CS low.

    ii) Made CS low.

   iii) Configured SPI in mode 2 after making CS low.

   iv) Sent Command (As per datasheet without any shift i.e A0 00 00 for reading ID register only)   

       Now I am receiving the expected response from ADC. But I don't think this is a good idea to change SPI mode again and again.

4) As per the datasheets of both ADC and MSP430FR5994

     i) ADC - a) Launches data on SCLK rising edge

                   b) Latches data on SCLK falling edge.

      ii) MSP430FR5994  SPI (MODE 1) - a) Launches data on SCLK falling edge

                                                                b) Latches data on SCLK rising edge.

By looking at the timing waveforms of MSP430FR5994 I came to the conclusion that :

i) In mode 1 the first edge (encircled by yellow  circle) is rising edge  and  the MSB is shifted out before rising edge. There is no falling edge on SCLK  when  MSB is shifted out  on SIMO  that's why the MSB is not latched by ADC (ADC needs falling edge to latch data )

ii) because ADC is missing MSB , it interprets Command as a wrong command and gives null command response. This is true because we are getting correct response (need to left shift by 1 bit , unable to figure out why I need to perform shifting operation) when we send command by shifting 1 bit right in SPI mode 1.

iii) I used SPI mode 1 before making CS low to fulfill criteria - CS transitions must take place when SCLK is low., After making CS low (High to low transition) I configured SPI in mode 2 .

iii) In mode 2 when MSB is shifted out on SIMO there is falling edge on SCLK (encircled by violet  circle) so MSB is getting latched by  ADC and we are getting expected response.  

     I want to know that is there any way to avoid changing SPI modes again and again. The 1 bit shifting method (1 right shift for command and 1 left shift for response data) also works but it adds complexity in firmware. 

Hi Prasad,

Please refer to section 8.5.1 of the ADS131M08 data sheet. This device only supports SPI Mode 1 (CPOL = 0, CPHA = 1). Both the host controller and the ADS131M08 must launch data on the SCLK rising edge and latch data on the SCLK falling edge. SCLK will idle low in this mode.

Can you please verify the timing specifications I mentioned in my previous reply?

Regards,

I provided enough delay more than 50 ns after cs transition from high to low.So that is not the problem.

Hi Ryan,

I will share the results after trying mode 0.I will  also create the thread on MSP430 E2E forum.

Hi Prasad,

Thank you for the update. I'm glad this resolved the issue for you.

Best regards,