Other Parts Discussed in Thread: ADS5463, ADS4249
I am using ADS5463EVM with 12 bit LVDS signals. Do you have perhaps a VHDL core for this LVDS transmiton? DDR or SDR are both great, but not serdess, as it is data receive with fast (500 Mbps) clocking - with short latency.
It is a proof of concept for fast ADC receiver with zero latency. Therefore we choose you ADS5463EVM as the ADC and if you have this core it will save us some efforts.
After review Tida00069 example, there is difference between ADS5463 and ADS4249 and this is the DRY function. I need further information ho to implement the DRY signal line, mainly because we intend to work with 500 MHz clock.
I would like to better understand the DRY synchronous with data and how to define if it works in DDR or SDR.
Thanks
