Other Parts Discussed in Thread: DAC3174,
Hi team,
Now our customer can output normal waveform, but if the temperature changes too much, there may be timing mismatch between FPGA and DAC data interface. After adjusting the register delay, it can return to normal. So our customer wants to use the internal IO TSET function of DAC chip to realize the interface timing verification. However, no matter how it is configured, the function cannot be used normally.
