Other Parts Discussed in Thread: DAC3482, , CDCE62005
For the DAC3482EVM, there is one register configuration file provided as a reference: "DAC3482_FDAC_1228p8MHz_4xint_NCO_30MHz_QMCon.txt"
This configures the DAC3482 and the CDCE62005 registers. The register CDCE62005 x3 entry in this file is defined as "C10C0003". When I review the CDCE62005 manual for this register, the specified bit settings are not consistent with the manual. Here is the relevant manual page from the CDCE62005 manual:
The value 0xC10C0003 translates to (for these subset of bits)
Bit 21 = 0
Bit 22 = 0
Bit 23 = 0
Bit 24 = 0
Bit 25 = 0
Bit 26 = 1
Bit 27 = 1
It is not clear from the CDCE62005 manual what the config file attempting to achieve. This bit mapping does not appear to be a valid combination. I believe this is important, because this clock Drives the FPGA clock pins, so I'm guessing its important.