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ADC128D818: ACK does not return

Part Number: ADC128D818

Hi Staff

Question
ADC128D818 may not respond to I2C access.
We believe that there are no particular problems with the SDA and SCL signal timing and waveforms.

・ SDA and SCL pull-up resistors are 5kΩ (Vcc = 3.3V)
・ 100kbps, rise time 0.9us.
・ SDA changes at the same time as the SCL falls, and the stable level of the SDA at the start of the SCL is read.
-NAK (High) is returned for write access to address 1D of this device. Inaccessible!

As a countermeasure,
if you connect CR (33k ohm + 2200pF) to SCL and connect it to GND,
normal operation will occur and NAK (Low) will be returned.

There is no difference in the signal waveform before and after connecting CR to SCL (check with an oscilloscope)

What is the reason why I2C does not work properly without connecting CR?
please tell me.

best regards
cafain

  • This question is being address on a different post

  • Cynthia san

    Thanks for your comment。

    It is different from the specified problem.

    If no CR is connected, NACK (High) is returned.
    (Communication NG)

    When CR is connected, ACK (Low) is returned.
    (Communication OK)

    The power supply for the device power supply (3.3V) and the pull-up resistor (1kΩ) is 3.3V.
    (Digital power supply is 3.3V and the same voltage)

    As a countermeasure,
    if you connect CR (33k ohm + 2200pF) to SCL and connect it to GND,
    normal operation will occur and ACK (Low) will be returned.

    There is no difference in the signal waveform before and after connecting CR to SCL (check with an oscilloscope)

    best regards

    cafain

  • Apologies, I though this was the same question. 

    The I2C Communication for the device is shown below. Not that data line SDA needs to be stable during both the rising and falling edges of SCL, and changes when SCL is low. 

    I suspect that since the the data is changing at the falling edge of SCL, when the RC is added, it slows it down just enough.

    Regards

    Cynthia

  • Hi, Cynthia san

    UM10204 I2C-bus specification and user manualthe following notes are written on page48.
    --------------------
    [2] tHD;DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.
    [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of
    SCL.
    --------------------

    I think the above is the content to be adjusted on the master IC (microcomputer) side.
    * Adjust the SDA timing on the master IC side.

    I don't think there is a circuit that delays the SDA of ADC128D818 by 300ns.
    Is there any problem with my recognition? The following notes are written on page48.

    regards
    cafain