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Original question:

DAC8718: device heating up (when negative voltage AVss applied)

DAC8718: Power supply sequencing

Paul Tomlinson1
Prodigy 40 points
Part Number: DAC8718

The user guide for the evaluation board suggests that the chip can be damaged by an incorrect power up sequence.

My question is, do I need to control power down sequencing to avoid damaging the chip?

  • 0
    TI__Mastermind 18546 points

    Hi,

    Please follow below power down sequencing if possible. I am assuming IOVDD and DVDD connected together.

    REF --> AVSS and AVDD ---> IOVDD and DVDD 

    If IOVDD and DVDD as separate rail, follow below sequencing

    REF --> AVSS and AVDD ---> DVDD --> IOVDD

    Similarly for power up sequence, you can follow the reverse order. Make sure REF comes last. It is advised to have a pull up resistor to IOVDD for the digital initialization pins (LDAC, CLR, RST, CS, and RSTSEL) to ensure that these levels are set correctly while the digital supplies are raised.

    Hope this clarifies your query. Let me know if you need more help.

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Prodigy 40 points

    Hi AK

    Thank you for your prompt reply.

    Controlling the sequence on power-up and controlled power-down could be done as there is a microcontroller on board, but ensuring the correct sequence is adhered to in the event of a depowering of the board might make this chip unsuitable.

    Thanks anyway. Paul T

  • 0 in reply to Paul Tomlinson1
    TI__Mastermind 18546 points

    Hi,

    Power up and down sequence maintains unnecessary latch up conditions for the device. Also we will have ESD diodes on REF pin to the supply voltages, If REF comes first before supply, ESD diodes can conduct causing huge power draw from the REF circuit. This is one example.

    So Please adhere to power up sequence for the device as per datasheet.

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Prodigy 40 points

    Hi AK

    I now understand the Vref input requirement. I assume the ESD diodes go to DVdd and GND.

    The relationship between IOVdd and DVdd is a little confusing.

    In the absolute maximum section of the data sheet. It says that IOVdd must be less than (DVdd +0.3v), but in the 'power on reset sequencing' it says that IOVdd should be applied before or at the same time as DVdd.

    Are there ESD diodes on the IOVdd supply pin or is a more complex problem.

    In the  'power on reset sequencing' it says AVdd should be applied after the digital supplies, and I can understand this for proper operation of the DAC. Will the IC be permanently damaged if the AVdd and AVss supplies are still present when the digital supplies are removed? I am trying to arrange the supplies so that this doesn't happen, but the 'hold up' times for the rails are determined by other loads.

    Regards

    Paul T

  • 0 in reply to Paul Tomlinson1
    TI__Mastermind 18546 points

    Hi Paul,

    IC will not be damaged permanently in any of the sequencing modes, you may encounter latch up condition and it persists more duration, you can have reliability issue with the device. As far as IOVDD and DVDD are concerned, IOVDD can be same as DVDD, that's the reason abs max shows up like that  ( Assuming IOVDD and DVDD are at same potential)

    if both are different, I suggest power up IOVDD first and then DVDD.

    Regards,

    AK