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ADS131M08: ADS131M08 Questions

Part Number: ADS131M08

I am considering the use of the ADS131M08 for a thermocouple based temperature sensor.  I have the data sheet for the part, but have a number of questions.

1. Section 8.3.5 of the data sheet indicates that the master clock should be synchronous with the SPI SLCK. Assuming we are using the onboard oscillator, how is this synchronization accomplished?
2. Can you recommend a 2.048 MHz crystal operating in the same temperature range as the ADS131M08?
3. The device requires both analog and digital power supplies. Is it possible to use one power supply for both?
4. Section 6.3 indicates that the digital supply can range from 2.7 to 3.6 V (3 V nominal). However, Section 8.1 implies that the digital supply should be either 1.8V or 3.3V. Which is right?

  • Hi William,

    Ryan, our primary support for this device is out of office today. He'll be back to address your questions in further detail on Monday. 

    3. Yes this should be fine. I recommend connecting AGND and DGND as close to the device as possible with a low impedance trace. 

    4. The suggestion for 1.8V or 3.3V is recommended simply because that is the voltage that most MCU's operate at. The digital voltage can be in the 2.7 to 3.6V range when DVDD is not connected to CAP. Then the digital LDO will step the voltage down to 1.8V which is the digital system voltage of the device. If DVDD is connected to CAP externally, then the digital supply bypasses the LDO to supply the 1.8V directly to the digital system. 

    For more information on these two questions, please see 10 Power Supply Recommendations. 

     

  • Alex answered 2 of my questions (3 and 4).  I am still waiting for answers to questions 1 and 2.

  • Hi William,

    I did a quick search for 2.048 MHz crystal oscillators on Digi-Key and only came up with a few options

    The synchronization between CLK and SCLK is not a strict requirement, but it can reduce some high-frequency noise from coupling through the ground plane and into the ADC inputs. This would only be possible if both clocks were sourced from the host controller and set to same frequency or some 1/2^n ratio.

    The device will still operate within the data sheet specifications without CLK and SCLK in sync.

    Best regards,