I have a customer who has the following question:
I am currently working on a project that is using your ADS1259 24-bit ADC and am running into an issue I was hoping you could help me with.
Below is our configuration code for the IC. The SPI bus is running at 4MHz, however I have also ran all the scenarios I will describe below at 2MHz with the same results. The write block contains the write command and number of registers to write minus 1 followed by the register data. The read block sends the read command and then the number of registers to read minus 1, and finally the stopRC command is used to stop the run continuous mode to ensure we can write to the IC. One aspect to point out is the 250mS delay at the start on the configure routine. This is to ensure we do not start writing to the IC until it has fully powered up and released the internal reset. 250mS is excessive but is what we are using in early development.
When configuring the device, we are writing the below values to the device registers:
Reg0: 0x05 – Rbias enabled, SCLK timeout enabled
Reg1: 0xC0 – Out-of-range flag enabled, checksum enabled, internal reference selected
Reg2: 0x05 – Gate control mode selected, 1200 SPS
Reg3: 0x00 – No offset correction
Reg4: 0x00
Reg5: 0x00
Reg6: 0x00 – No full-scale correction
Reg7: 0x40
Reg8: 0x00
and the read back is:
Reg0: 0x25 – Factory ID Info, Rbias enabled, SCLK timeout enabled
Reg1: 0xC0 – Out-of-range flag enabled, checksum enabled, internal reference selected
Reg2: 0x45 – External Clock selected (this is correct, we have an external crystal), Gate control mode selected, 1200 SPS
Reg3: 0x00 – No offset correction
Reg4: 0x00
Reg5: 0x00
Reg6: 0x00 – No full-scale correction
Reg7: 0x40
Reg8: 0x00
One aspect I noticed is that bit 7 in register 0 is supposed to always return a 1 and is a read only register. In the readback in software bit is returned as a 0.
After configuring the IC and looking at the readback which look ok, we set the start pin high to begin the 1200 SPS conversions. The DRDY pin behaves as expected at this point and can be seen in the “DRDY 1200 SPS” waveform in the attached zip file. The DRDY line is pulled low every 1/1200 seconds and is pulled high on what is presumed to be the first SCLK edge which is in line with the description of gate control mode in the datasheet. The DRDY pin feeds into a digital input pin on our processor that is being used as an interrupt to read the data each time a new conversion is ready. Below is the code that handles this read:
The main issue occurs at this point when an external supply is applied across AINP and AINN. When this voltage is applied, the conversions stop altogether. From our testing, the voltage level across AINP to AINN is irrelevant as long as it is above GND. This can be seen in the waveform labeled “DRDY behavior when AINP supplied” in the attached zip file. When running the MCU in debug mode and monitoring the rxBuffer (storing the read data from the IC), the value read appears to be correct at the point where conversions stop but no more data can be read after as the DRDY line is always high. After turning off the external supply, turning off the supply to the MCU/ADC, then turning the supply to the MCU/ADC back on, the DRDY line looks to behave correctly again until the external supply is applied to AINP again.
Also in the zip file, there are waveforms showing the behavior of the various supplies (AVDD, DVDD, VREFP) when the supply to AINP is applied. All these supplies look fine and shown no strange behavior at this point. Additionally, there is a waveform labeled “CS and SCLK” that shows the chip select is held down the entire time data is being read back. There is about a 10 uS delay between the CS being pulled low and the first clock edge which should be in spec with the IC. Also, this time is similar to the time between the DRDY being pulled low and the first clock edge so that should be in spec as well. Below is a screenshot of the IC circuitry that is currently implemented on our PCB. Two things to point out are the Reset line has been modified to be pulled high at all times and the SYNCOUT pin has been modified to be pulled down with a 1MOhm resistor as described in the datasheet.
One last thing to note is if I set the SPS to the default 10 SPS, the conversions do not appear to stop, DRDY continues, when the AINP is applied, however, the data being read form the IC jumps around significantly and then latches to 0x7FFFFF which corresponds to the full scale Vref.
I am currently stumped as to why this would be occurring and was wondering if you could help with the issue or could put me in touch with someone who could help. Below are some more behaviors seen that are not quite as expected either.
In regards to the DRDY behavior in gate control mode, it is supposed to be pulled high on the first rising clock edge after it is pulled low. The waveform “DRDY and SCLK” shows the first set of clock pulses, being the read command, do not reset the DRDY line high. It is not until the first set of data out from the IC when the DRDY is pulled high. Additionally, looking at the “DRDY reset on SCLK falling edge” waveform, the DRDY line appears to be resting on the falling edge rather than the rising edge as described in the datasheet. Is there a reason this may be?
Thanks in advance for your help.
