Part Number: ADC124S101
I'm driving the ADC using a system that can only change the output pin states synchronously to the falling edge of the SCLK clock. The SCLK is not stopped with the #CS going high, because other devices need to be scanned with same clock in parallel.
Now, the datasheet states:
"When CS is brought high, SCLK is internally gated off. If SCLK is stopped in the low state while CS is high, thesubsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the trackmode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is stopped with SCLK high, the ADCenters the track mode on the first falling edge of SCLK after the falling edge of CS."
What would be the behavior if both #CS and SCLK are changing at the same time? Would it be unpredictable, or is the previous value of SCLK (high) still in effect when #CS going high is recognized?
Any hints are highly appreciated.
If CS and SCLK are acting the same, meaning the device sees a falling edge of CS and SCLK at the same time, the device will enter track mode at this moment.
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In reply to Cynthia:
thanks for your reply.
Yes, for the falling edge of CS the datasheet somehow describes this case (Figure 6 with Tcsu and Tclh both equal to 0.5 Tsclk) and it is good to know that this is indeed a legal case.
What is actually unclear to me is the rising edge of CS and the falling edge of SCLK at the same time, and how to interprete the quoted text from the datasheet in this case. Sorry I did not make that clear enough.
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