ADS52J90EVM: ADC register readback not working over SPI - Part 2
Part Number: ADS52J90EVM
I'm evaluating the ADS52J90EVM board with the TSW14J56 FPGA board. I can run the High Speed Data Converter pro software which opens up the HMC-DAQ GUI. I load the ADS52J90 firmware onto the FPGA. And in HMC, I choose the "JESD: 16ch 16x 14b 4ADC/Lane" option. And everything works, whether with a ramp or analog input. That's great!
But when I dig into it, I'm confused. These default settings are supposed to be running JESD402B, subclass 1. When I check the registers, that's what I see (ADS52J90 register 0x55 and 0x73 are both 0, which means it should be running JESD402B, subclass 1). But I can't physically observe a SYSREF clock going to the ADS52J90.
When I probe the outputs, DCLKOUT0 and SDCLKOUT0 seem to be working fine. I see the clocks on TP4, TP5, TP6, TP7 on the eval board. DCLKOUT2 works as well. I can see the clock on JP40, and have the header supplying that to the ADC.
However, I see nothing for SDCLKOUT3 (ADC_SYSREFP_LMK for example). I prove on JP41, all pin inputs, and see nothing. When I capture the data, which shows up correctly in the GUI, I still see no ADC SYSREF activity, no one-shot, no pulse, no continuous, nothing.
So my main questions is, how is this working? If the ADC is using JESD402B, subclass 1, the SYSREF clock is required, right? Or does it have ways to mitigate not receiving any such clock. Do I have a faulty LMK04826 part? Or is this how the default settings are supposed to be? JP4 is installed, so I'm supplying the LMK04826 with OSC1 into OSCIN. For the status LEDs on the eval board, only D5, D6 and D7 are lit up. D1-D4 are off.
What's going on here?
SYSREF clock is required per JESD204B standard to maintain expected dertministic latency.
SYSREF can be an pulse or reptitive wave. for less interface, pulse is used often. So when it is pusle, you may not be able to capture it. when you use repeitive SYSREF, the freq needs to be way off RF signal.
it is possible that JESD capture is still OK without SYSREF present, while the determinsitc latency is not there.
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