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ADS131E06: Overrange detection

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Part Number: ADS131E06

Hi,

I am using an ADS131E06 converter configured for 4V internal reference and it is powerd by +-2.5V supply. The input signal normally is between +-4V differential voltage symmetrically to Vss.

Sometimes I get strange readings, no idea why.

I use channel 0 which gives me 07 ff ff readings for thousands of samples ==> signal out of range. The status word is c0 00 e0.

Normal sample looks like 0a 1e cb for instance and status word c0 00 e0 (no typo!!!).

What did I expect: Different values of the status word, because the channel 0 of the ADC is not overloaded in the second example and overloaded in the first sample.

Is there anything to setup? I read out of the paper, that the limits for the fault comperators were set to 95% & 5% by default.

Another question: When I am sampling ac signals symmetrical to Vss cause I use +- 2.5V supply, the signal is < 5% of the input range around crossing Vss level. Is the comparator fired in this situation?

Or is the p-input compared to +Vref and the n-input compared to -Vref only to detect signals with a common mode component out of range?

In the moment I get hundreds of thousands correct readings but suddenly the ADC saturates. I measure 3 signals from different sources (different input stages on different PCBs) and if the problem occurs, all three channels give bad readings (saturating, but status info ok).

I have to switch the polarity of my signals and after measuring the reversed signals the channels saturate at 08 00 00. So looks like the signals where out of range and the ADC is working well.

Thanks for helping.

  • Hello Gerhard,

    Thank you for your post.

    Can you clarify what the common-mode voltage is for your input signal? You mentioned that is it symmetrical around Vss (-2.5 V?). However, for bipolar supplies, the input signal common-mode voltage should be near 0 V (GND) in order for the signal to swing symmetrically above/below ground while staying within the absolute input voltage range (AVSS to AVDD).

    The input overrange comparators are looking at the absolute voltage on each pin with respect to the supplies (AVDD and AVSS). These comparators do not consider the differential voltage into the device. There is nothing to configure other than the relative threshold voltages.

    What is the PGA gain setting used in your measurements? The differential input voltage limit is +/-VREF/Gain. Beyond this voltage, you will see +FS and -FS code readings from the ADC channel.

    Regards,


    Ryan Andrews

    Applications Engineer | Precision ADCs 

    Are you working on a bio-potential application? Check out these helpful resources: ADS129x BIOFAQ | ECG Online Training

  • In reply to Ryan Andrews:

    Hi Ryan,

    AVss = -2.5V

    AVdd = 2.5V

    VRefN = -2.5V

    The signal is symmetrical to AGnd and AGnd is the mis of +2.5V and -2.5V.

    The measured differential voltage is ok.

    The overflow bits for the channels with external signals were 0.

    The positive overflow bits of channels with internal test signals were 0.

    The negative overflow bits of channels with internal test signals were mostly 1, sometimes 0.

    Testsignals:

    channel 1: Short, giving ~ -2mV

    Channel 2: Vdd, giving ~ 3.29V (nom. 3V3 supply.

    With best regards

    Gerhard

  • In reply to Gerhard Kreuzer:

    Hi Gerhard,

    Thanks for the update.

    The input overrange comparators are part of the default MUX[2:0] signal path. This would correspond to the left side of Figure 16, but the overrange comparators themselves are not shown. When MUX[2:0] is set to 101 for the internal test signal, or when MUX[2:0] = 001 for internal short, these overrange comparators and the INxP and INxN pins are disconnected from the PGA. This means they will be floating and their results can be ignored.

    Regards,


    Ryan Andrews

    Applications Engineer | Precision ADCs 

    Are you working on a bio-potential application? Check out these helpful resources: ADS129x BIOFAQ | ECG Online Training

  • In reply to Ryan Andrews:

    Hi Ryan,

    ok, this is the answer.

    But: It is not nice to left the comperators out in Fig. 16. Maybe somebody can update the documentation?

    And, it would be a nice feature to set both overflow bits when a test signal is connected to the ADC to tell the user 'Hey, this is not a real world signal!'. The user will know, that internal signals shouldnt overdrive the ADC.

    To let signals floating is never a good idea, isn't it?

    With best regards

    Gerhard