Hello team,
I think ADS8912B can work with 1.8V interface by supplying 1.8V as DVDD. Is it correct?
Datasheet 6.3 Recommended operating condition mentions two conditions, "Operating" and "Specified throughput".
What is "Specified throughput" meaning?
Best regards,
Hello Sato-san,
Yes, the ADS8912B can work with a 1.8V interface (1.65V minimum). However, the digital cells will not support the maximum SCLK frequency under all conditions when the interface voltage drops to less than 2.35V. Under certain modes, the reduced SCLK frequency may not be high enough to support the full 500ksps data rate. However, there are many options to get around this limitation.
The reduced SCLK frequency for supply voltages less than 2.35V is listed in the datasheet specifications section. Notice that the maximum logic low level must be less than 0.2DVDD and the minimum logic high level must be greater than 0.8DVDD to support a maximum SCLK frequency of 20MHz. If you have a local SCLK buffer that can drive the SCLK input with logic levels of V-IH>0.9DVDD and V-IL<0.1DVDD, then the device will support up to 68MHz SCLK, which is close to the maximum of 70MHz with DVDD>2.35V.
If you are using a single SDO SPI interface and are limited to 20MHz SCLK maximum, you can still support the full data rate when using the zone 2 data transfer. These details are shown in Figure 46 and equations 5 to 10 of the datasheet.
As an example, using zone 2 data transfer, the maximum data transfer time (the time available to clock the conversion result out of the device during the data cycle period), is give by equations 8 and 9.
t-read_Z2 <= t-cycle - t-d_cnvcap - t-qt_acq (8)
t-cycle = 2000nS (500ksps sample rate)
t-d_cnvcap = 20nS
t-qt_acq = 30nS
t-read_Z2 <= 2000nS - 20nS - 30nS = 1950nS
F-SCLK >= 18/t-read_Z2 (9) where 18 is the number of bits to clock out for the conversion result.
F-SCLK >= 18/1950nS >= 9.3MHz
Regards,
Keith Nicholas
Precision ADC Applications
