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ADS7066: SPI Timing

Gordon McKenzie
Intellectual 580 points
Part Number: ADS7066

Hello,

I'm trying to get the ADS7066 running on a new design, and I've come across an issue that I can't figure out.

On the front page of the datasheet, it says that full throughput can be achieved with a SPI frequency >4.5MHz.

Section 6.7 gives limits of 3200ns for t_conv and 800ns for t_acq.

The timing diagram at the top of the following pgae (page 8) shows the chip select being held high for t_conv (min 3200ns), then going low for t_acq (800ns). It is during this t_acq that a conversion result is passed out to a host. So if all the SPI activity takes place in 800ns and each sample is 16 bits (leanest data possible, no averaging or flag bits), the min time per bit is 800ns/16 = 50ns, yes? This in turn means that in order to achieve full throughput, SPI frquency has to be >20MHz and to clock out the full 24-bit packet in 800ns needs >30MHz.

So, where does the figure of 4.5MHz come from? Presumably there's something I haven't taken into account or something I haven't properly understood (or maybe a typo in the datasheet). My host is a low-power FPGA so although 30MHz should be achievable, it would simplify things (and reduce power) if I were able to slow the clock down to <10MHz.

An explanation to clear this up would be very helpful.

Thanks,

Gordon.

  • 0
    TI__Expert 3675 points

    Hi Gordon,

    The minimum CS high time (tWH_CSZ) is 220 ns. This means you can pull CS low and start reading previously completed conversion result while the ADC is still converting the analog voltage sampled on CSz rising edge.

    When tCYCLE = 4 us (i.e. 250-kSPS), the host would get 3.76-us to read the 16-bit conversion result (tCYCLE - tWH_CSZ - tQUIET = 3.76 us).

    In this way of reading conversion result from the ADC, the ADC will output the previously completed conversion result (1-cycle latency) while the ADC is still converting the analog input sample. You may notice increase in noise this mode.

    I hope this helps.

  • 0 in reply to RahulVK
    Intellectual 580 points

    Hi Rahul,

    thanks for your explanation - it's all clear now. I hadn't appreciated t_conv and t_acq were not set directly by the high/low times of CS, but following your explanation the diagram in thedatahseet is now very clear. Thanks for your quick reply to resolve this.

    Gordon.