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DAC3484: Single Channel Maximum Bandwidth
Part Number: DAC3283
My design requirement is to generate Fout = 37 MHz. from the DDS . DAC 3283 is interfaced to xilinx FPGA. The interface is 8 bit LVDS.
DDS sampling clock is 96MHz.
DAC clock is 192 MHz.
Data clock is 192MHz..
Can i run DDS sampling clock at 192MHz to get the Fout as 37MHz?
Thanks in advance
what is the data rate and interpolation rate from baseband you are planning on using? I believe it is 96MSPS based on your description above. This is 2x interpolation.
The FIR filter at the DAC input has 80% roll-off in complex domain, or 40% roll-off in real domain. With 96MSPS, the real signal bandwidth is 96MSPS*0.4 = 38MHz. Your signal is close to the filter edge.
You will need to use matlab to simulate the filter taps listed on the datasheet to perform simulation to see if the FIR filter on the DAC interpolation is sufficient for your application.
6724.DAC3282-3 Byte Wide DDR Clocking.pdf
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In reply to Kang Hsia:
FIR0 filter is enabled. It is 2X interpolation. The information given in the PDF clearly indicates the relationship between the data clock, DAC clock and interpolation factor.
1) If we are not using 2X interpolation then due to the interleaving of channel A and B the data clock frequency shall be increased by 2 times the DAC clock frequency ?
In reply to Ravi Kanth:
If you have 1x interpolation for wider bus, then your interface data bus has to be increased by 2x to accommodate the higher input data rate
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