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Original question:

ADS54J69: minimum device clock frequency

ADS54J69: Dynamically changing sampling clock and configuring of decimation-by-2 filter

Ramesha A
Prodigy 110 points
Part Number: ADS54J69
Other Parts Discussed in Thread: ADS54J60, , ADS54J66

I want to switch operating condition at 5ms time interval between :

  • 230MHz clock with Decimation-by-2 filter i.e. 130MSPS.
  • 500MHz clock without Decimation-by-2 filter i.e. 500MSPS.

In this scenario -

  • Will this clock and decimation-by-2 filter change be feasible?
  • How much time JESD interface takes to stabilize with change of clock frequency?
  • Will the ADC performance specs be same and stable i.e. SNR of 73dBFs and SFDR of 93dBc at 230MHz/130MSPS clock frequency.

with regards

Ramesha

  • 0
    TI__Guru* 91947 points

    Ramesha,

    The clock and decimation filter will be feasible. Since the ADC serdes PLL frequency will change, you will have to reset the PLL, which will require two SPI writes. This will be the majority of the delay. The link will also have to be re-established. This will be about 140 ADC clock cycles plus whatever the FPGA is adding.

    The performance should be about identical if sampling at 500Msps or 230Msps.

    Regards,

    Jim 

  • 0 in reply to jim s
    Prodigy 110 points

    Jim,

    Our support team is not clear about disabling of decimation filter. Please explain give us more details about it.

    with regards,

    Ramesha

  • 0 in reply to jim s
    Prodigy 110 points

    Jim,

    What will be the Performance(SNR, SFDR, SINAD & ENOB) at clock frequency-250MHz and Center Frequency-70MHz.with ADC54J69(125MSPS) & ADC54J60(250MSPS).

    with regards,

    Ramesha A

  • 0 in reply to Ramesha A
    TI__Guru* 91947 points

    Ramesha,

    There was some confusion with the reply. I was trying to state you could operate the device in decimation mode with the two frequencies you mentioned. This device does not have a bypass mode, only a 2x decimation mode. If you need to operate without decimation, you could use the ADS54J60. Both parts offer the same performance. The main difference is the ADS54J60 has a bypass option and a few other decimation modes. See the data sheets for more info. Sorry for the confusion.

    Regards,

    Jim  

  • 0 in reply to jim s
    TI__Guru* 91947 points

    Ramesha,

    The data captured is as follows using a 491.52MHz clock:

    Mode          SFRD     SNR     ENOB     SINAD    (all in dBFs except ENOB)

    Bypass       84.2        71.2      11.5        71.1

    2x Dec        93           74         12           74.5

    You cannot capture 70MHz IF data with a 125MHz data rate as the decimation filter will cut it off. The Nyquist range for this mode 0 to 62.5MHz.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Guru* 91947 points

    Ramesha,

    I just remembered that if you use the high pass filter mode, you can capture this data with decimation mode. The new data captured below is using a 245.76MHz clock:

    Mode          SFRD     SNR     ENOB     SINAD    (all in dBFs except ENOB)

    Bypass       76           69         11.2        69   

    2x Dec        77           71         11.6        71.7

    I did not have access to a 250MHz clock source when doing this test. The data would be slightly better at 250MHz for the 2x decimation mode as the tone would move farther away from filter stop band region.

    This data was taken using the EVM on-board clocking. At 245.76MHz, the LMK output is not optimized which is also degrading the performance compared to the 491.52MHz test case .

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 110 points

    Jim

    Thank you very much for clarification of decimation configuration (i.e. only in ads54j60 bypass & decimation  is possible)  and providing  the results of ADC.

    Please tell me above results are using ADS54J60 chip only?

    Thanks

    With regards

    Ramesha

  • 0 in reply to Ramesha A
    TI__Guru* 91947 points

    Ramesha,

    Yes, only the ADS54J60. The ADS54J69 uses the same core as the ADs54J60 so the decimation results would be the same.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 110 points

    Jim

    Why performance is different for clock246MHz with bypass(snr69) and clock491MHz 2x decimation (snr74) even though same chip i.e.ADS54J60.

    If I get SNR74@2x (for 5MHz bandwidth) and SNR71@Bypass (for 240mhz bandwidth) with ADS54J60 then I am satisfied to use this chip for my application.

    with regards

    Ramesha

  • 0 in reply to jim s
    Prodigy 110 points

    Jim

    We need total 4 ADC channels. Since Sync between two ADC54J60 is little risk. If I use ADS54J66 will I get similar performance? 

    Please give us test results for sampling clock of ~500MHz & center frequency 70MHz, with decimation and without decimation for ADS54J66. 

    with regards,

    Ramesha A

  • 0 in reply to Ramesha A
    TI__Guru* 91947 points

    Ramesha,

    See test results in attached file.

    Regards,

    Jim

    ADS54J66_491p52Msps_bypass.pptx

  • 0 in reply to Ramesha A
    TI__Guru* 91947 points

    8585.ADS54J66_491p52Msps_bypass.pptxRamesha,

    The data is attached.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 110 points

    Sir

    Please give us data for 2 tone (with input frequency 69.75 and 70.25MHz) SFDR of ADS54J66 and ADS54J60 .

    With regards

    Ramesha

  • 0 in reply to jim s
    Prodigy 110 points

    Sir

    Slight correction - Feed input to ADC through power combiner 69MHz and 71MHz. Send us plots and Data.

    With regards

    Ramesha

  • 0 in reply to Ramesha A
    TI__Guru* 91947 points

    Ramesha,

    Decimate mode, bypass mode, or both?

    Regards,

    Jim 

  • 0 in reply to jim s
    Prodigy 110 points

    Sir,

    For bypass, decimation-by-2, & decimation-by-4 with ADS54J66 & ADS54J60.

    with regards,

    Ramesha

  • 0 in reply to jim s
    Prodigy 110 points

    Sir,

    Thanks for the earlier reports.

    The data given is for input signal of -7dBFs strength. Please provide Results of ADS54J60 & ADS54J66 in bypass, 2x & 4x decimation for input signal strength of 5dBm, 8dBm and 10dBm.

    with regards,

    Ramesha A

  • 0 in reply to Ramesha A
    TI__Guru* 91947 points

    Ramesha,

    All data sheet test data is normally taken with an input at -1dBFs with single tone data and -7dBFs with two-tone inputs. At 0dBFs, the device will be at full scale and start to show distortion. This will only get worse with the power levels you are suggesting.

    Taking this data is very time consuming and I do not have the bandwidth to do this right now. May I suggest you order these EVM's so that you can take these measurements yourself.  Otherwise, it may be some time before I can get this information to you.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 110 points

    Sir,

    For a critical program we have to finalize ADC part number. At least give us two tone data of ADS54J66 with 2x & 4x decimation for -5dBFs & -1dBFs.

    with regards,

    Ramesha A

  • 0 in reply to Ramesha A
    TI__Guru* 91947 points

    Ramesha,

    I was able to capture the data for you. When using two tones, the max amplitude used should be -7dBFs, otherwise the ADC will saturate. I do not think you want data wit the input at -5 and -1dBFs per your request. To prove this I did captures at -2dBFs and -5dBFs. I think you wanted data at -8dBFs and -12dBFs, which is what I captured. All of this is in the attached file.

    Regards,

    Jim

     ADS54J66_491p52Msps_bypass_new.pptx