ADS131E08: Using ADS131E08 Dev Kit. ADC CONFIG Registers Read Back correctly. However, ADC RDATAC mode continuously returns same Incorrect Values

Prodigy 150 points

Replies: 4

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Part Number: ADS131E08

Hi There,

Long story short, I am able to write to the CONFIG registers and read them back. But when going into RDATAC mode, the ADC does not report correct data when sampling. Every channel gets stuck at one value and consistently repeats that value on every DRDY falling edge cycle.

At this point I am unsure If I set something up wrong the PDK dev kit on the analog side. Or if there is a config setting issue so the ADC is getting hung.

I am using the ADS131E08-EBM-PDK Kit. I have the top board removed and the SPI signals, DRDY and reset input are wired an FPGA Development kit.

The ADS131E08 Dev kit has 5V to power the board and 3.3V provided for the DVDD rail as well. The 3V unipolar analog supply is chosen with the jumpers. The external oscillator is enabled and 2.5V is connected to VREFP for use as an external reference. I have +1.25V connected across channel 1 and the rest of the inputs are left floating.

The FPGA uses a 80 ns SCLK and follows the TCLK delays asked for in the datasheet. I split everything into 8 clock cycles and inserted TCLK delay after each byte. The SCLK only runs during the write/read cycles.

The process I am following to enable the ADC is:

  1. Power Up ADC. (ADC RESET is held high, START is held high)
  2. Wait for VCAP to Settle
  3. Issue a Reset pulse and wait for 18 TCLKS
  4. Send the SDATAC Command
  5. Read CONFIG2, Receive a 0xE0 as expected
  6. Write 0x40 to CONFIG3 (use external reference)
  7. Write 0xE4 to CONFIG2 (Disable test signals)
  8. Write 0xD6 to CONFIG1 (Set Rate to 1K)
  9. Read CONFIG3= 0x41 (datasheet says LSB bit is reserved and can come back as 1 or 0)
  10. Read CONFIG2= 0xE5
  11. Read CONFIG1 = 0xD6
  12. Set the START signal High (Keep high forever now)
  13. Wait for 4 TCLK cycles (Do I need to wait longer here, or does it matter since DRDY will not go low until ready?)
  14. Send the RDATAC Command
  15. Wait until DRDY goes low
  16. Sample the ADC every time the DRDY goes low. (I have confirmed the correct 216 clock cycles every time on each sequence)
    1. For the STATUS->I get back 0xC0F000 (Correct ID, Says Inputs 1-4 are faulted where voltage is in range or there is no voltage applied at all?)
    2. Channel 1 reads back 0x640000
    3. Channel 3-4 reads back 0x800000 consistently
    4. Changing the input voltage on these channels doesn’t make a difference. It always reports back the same

Another observation I had, is when I read the ADC outputs the next registers data on the next SPI cycle when asking to only read one channel. It doesn’t affect me, but it seems like this is faulty behavior of the ADC.

I have included some marked up screenshots that show a successful config read, the strange next registers data on the next CS cycle and the ADC sampling.

4 Replies

  • Hi Tony,

    Thank you for your post.

    Your startup routine seems correct. I assume that the registers to which you are not writing are left alone as defaults? Can you please do a complete register read to confirm? The voltage that is converted by the ADC channels is dependent on that channel's MUXn[2:0] setting (see CHnSET register).

    When you apply an input voltage to any of the channels, it is important to maintain the input common-mode within the range given in the data sheet. The common-mode is the average voltage seen on both INxP and INxN and is typically held near mid-supply. What is connected to IN1N in your test?

    Regards,


    Ryan Andrews

    Applications Engineer | Precision ADCs 

    Are you working on a bio-potential application? Check out these helpful resources: ADS129x BIOFAQ | ECG Online Training

  • In reply to Ryan Andrews:

    Hi Ryan,

    You are correct, I am leaving the other registers as defaults. As for the IN signals, i have AVSS tied to the negative input and 1.25V connected to the positive input. I tried this on channels 1 and 2. If I measure INP with respect to INN it measures 1.25V. If I measure INP with respect to AVSS I measure 1.25V. If I measure INN with respect to AVSS I measure 0V. AVSS is tied to AGND as well in this unipolar dev kit situation. I don't see an issue with common mode voltage here. I don't see a change in the read back values if I remove the 1.25V or increase/decrease the 1.25V, it always comes back with the same wrong value.

    Another data point to mention that I didn't have earlier in the post. The DRDY signal is pulsing at 1KHZ as expected.

    I went ahead and read all the the registers. The CHnSET registers are coming back correct as 0x10. Here is an example of a correct read:

    I am finally seeing something strange here with the ID Register. Every other register looks correct expect this one for default.  I am getting back a 0xBC, which shouldn't be possible (datasheet says 0xD2). The upper nibble is right, but the lower nibble doesn't amount to anything. I saw other posts on the forum that complained about the ID register coming back as 0xD0 (in 4-channel mode). This doesn't appear to be the same issue since both nibbles are incorrect. Bit 6 should be high and Bit 5 should be low, but they are reversed. Also bits 3 and 2 in the lower nibble should always be 0 and I am reading back a 1 on each of those bits. Let's say it was in 4 channel mode, Channels 1 and 2 should work, which isn't the case.

    The ID is wrong, while everything else is working so I am starting to wonder is this converter somehow powering up in some factory test mode? 

    In addition, I have reviewed the power up timing, since some of the forums talk about that, and the timing is met with margin. Here's what i am doing:

    1. Install the JP4 jumper to keep the PWDN signal pulled low
    2. Power up AVDD ( I have tried bringing AVDD/DVDD up at the same time as well)
    3. Power up DVDD
    4. Wait seconds
    5. Remove Jumper
    6. Wait seconds
    7. Tell FPGA to run the reset-> configuration routine
      1. FPGA starts high on reset then waits for 22 us then goes low for 1 us and comes back high for 22 us before the first SDATAC command is sent

    Here's the faulty ID read: 

  • In reply to Tony Spagnolia1:

    Hello Tony,

    Generally, the ID register reads back incorrectly when the POR (power-on reset) procedure is not followed. However, it seems like you are doing it correctly by waiting for the supplies to ramp and issuing a RESET pulse. The internal default oscillator (CLKSEL = 1) is 2.048 MHz, so 1 us should be plenty for the device to recognize the RESET pulse. There is no need to hold the PWDN pin low using the jumper while the supplies ramp, but it should not have any impact.

    Have you tested other devices to see if the behavior is consistent? If you restore the EVM back to factory default jumper settings and pair it with the MMB0 motherboard that shipped with it, does the EVM software read back the same ID value?

    Regards,


    Ryan Andrews

    Applications Engineer | Precision ADCs 

    Are you working on a bio-potential application? Check out these helpful resources: ADS129x BIOFAQ | ECG Online Training

  • In reply to Ryan Andrews:

    Hi Ryan,

    I moved onto using the software and the motherboard as you suggested. Unfortunately, the software isn't able to read any of the registers correctly. I am not sure if I have a jumper settings or if I have a bad board.

    I did verify that the motherboard is sending the CS/SCLK and DIN lines. I tried resetting, powering down, re-installing the software but continued to receive the same results. 

    My jumper settings are (I believe these are the default):

    • JP1- 1-2
    • JP3: Installed
    • JP4: Removed
    • JP5: 2-3
    • JP6: 1-2
    • JP7: 2-3
    • JP8: 1-2 (I Tried 2-3 as well)
    • JP9: 2-3
    • JP10: 1-2
    • JP11: 2-3

    This was the the value after the tool loads up and syncs:

    Then this is the value after I run the Refresh registers command: