Other Parts Discussed in Thread: DAC38RF82, DAC38RF80EVM
1. On DAC38RF82EVM, CMODE1 is PLL in Distribution Mode, right? Which is using external clock, for example 6144MHz for both DAC and PLL CLKin1.
By setting PLL1 CLKin1 Out MUX to Fin and PLL2 VCO MUX to External VCO, CLKoutx can be programmed as desired.
2. In firmware A10_DAC38RF82_7p68G_84111, the FPGA device clock is 192MHz that sets the lane rate at 7680Gbps.
What should the SYSREF frequency be? Thank you.