This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC38RF82EVM: clock mode

Part Number: DAC38RF82EVM
Other Parts Discussed in Thread: DAC38RF82, DAC38RF80EVM

1. On DAC38RF82EVM, CMODE1 is PLL in Distribution Mode, right? Which is using external clock, for example 6144MHz for both DAC and PLL CLKin1.

By setting PLL1 CLKin1 Out MUX to Fin and PLL2 VCO MUX to External VCO, CLKoutx can be programmed as desired. 

2. In firmware A10_DAC38RF82_7p68G_84111, the FPGA device clock is 192MHz that sets the lane rate at 7680Gbps. 

What should the SYSREF frequency be? Thank you.

  • New2day,

    For #1, you are correct. But the clock on SMA J1 that goes to the LMK first goes through a divide by 4 device. So the LMK CLKIN1 is always /4 of the DAC CLK in this mode. The divider is required as the LMK max input clock frequency is 3GHz.

    For #2, Max SYSREF frequency is (DAC CLK / Interpolation) / (K * N) where N is a whole integer. Another way to look at this is DAC Data rate / (K * N).

    Regards,

    Jim 

  • Hi Jim,

    On page 132 of the datasheet, it says that the SYSREF Freq = (Sampling Clock Freq)/N

    N = LCM(CLKJESD_DIV, 4xKxF). N is the least common multiple of 4xKxF and CLKJESD_DIV

    In the example on the same page,

    it seems that the Sample Clock Freq 4.9152Gsps is DAC Data Rate x 2 ( 2 is interpolation rate) while 80 is the common 4xKxF in mode 41121 when K =20. 

    I'm confused.

    1. Looks like SYSREF Freq has nothing to do with CLKJESD_DIV.

    So what was CLKJESD_DIV for here? 

    Did this mean that CLKJESD_DIV = 4xKxF? 

    2. the description on page 132 differs from  (DAC CLK / Interpolation) / (K * N) or DAC Data rate / (K * N). 

    But since interpolation rate is an integer, so calculated SYSREF Freq will work. Thank you.

  • New2day,

    There are several ways you can calculate this but I find the easiest method is what I sent. I did not write the data sheet and this is confusing to me as well.

    I would suggest leaving CLKJESD_DIV, DAC sample rate and interpolation out of the equation and just use SYSREF = [(Lane Rate) / (10 * F * K)] / N with N a whole integer.

    See attached for more ways of looking at this.

    Regards,

    Jim

    3073.bit rate calculation.docx

  • Hi Jim,

    #1 Questions about SERDES_REF and SERDES_CLK,

    For lane rate 7680Gbps, the SERDES clock on the FPGA side is 3840MHz, in case of CMODE1 (DAC PLL bypass):

    1. Should the SERDES_CLK also be 3840MHz? It looks like 4 modes, 00, 01, 10 and 11 according to Table 2.

    2. Would SERDES_REF be 384MHz when DACCLK = 6144MHz, SERDES PRE_DIV = 4 and DIV = 4?

    3. Would SERDES_CLK also be 384MHz if ENDDIVCLK = 1 (DIV =5) and MPY = 5 as default from GUI?

    4. If I like to have 3840MHz SERDES_CLK, I need to set MPY = 10x and set ENDDIVCLK = 0 (no DIV 5), right? 

     

    #2 SERDES PLL LED (or indicator) from GUI (DAC PLL bypass)

    Should both SERDES PLL LED be OFF for normal operation? 

    Thank you.

  • 1. The serdes clock must be between 1.5625 and 3.125GHz. The reference clock must be between 100 - 800 MHz. With MPY set to 5, and the GUI is set to use full rate, so the serdes clk = 0.25 * lane rate = 1.920GHz. Since MPY 5, and the serdes PLL = MPY * reference clock, this is also = 1.92GHz. All of this info can be found in section 8.3.2 of the data sheet.

    2. Yes.

    3. No. See answer in #1.

    4. You cannot have a serdes clk = 3840MHz as this exceeds the range of the PLL. See answer in #1.

    If the device is using 2 slices for the serdes lanes, then both Serdes PLL lock LED's should be off for normal operation. This is the default for this configuration when using the GUI.

    Regards,

    Jim 

  • Hi JIm,

    It's very helpful. 

    About SERDES PLL LED, I got a TSW14J56 EVM to test with. 

    The data is flowing and output is fine. 

    However both LED are also ON. It's Mode 84111 with DAC CLK 6144MHz, Dual DAC, 1 IQ pair, 4 lanes, 16x at 384Mbps sample rate and 8x at 768Mbps sample rate. 

    There is message about Rincewind1/0:

    PLL in the Rincewind0 block goes out of lock. A false alarm is generated at startup when the PLL is locking. User will have to reset this bit after start to monitor accurately.

    Could not find associate info from the sheets. 

  • New2day,

    The LED's are on by default You must click on the LED's and they should turn off if they are locked. Where did you see this message about Rincewind?

  • Hi Jim,

    It's ON again by clicking on the LED. They are OFF only when no SERDES lane were enabled.

    The message about RinceWind are from Alarm Monitor window. Thank you.

  • I do not see this issue with my setup. Increase the clock amplitude to 16dBm.If this fails, try another clock source. Not sure why you are having this issue.

    Make sure the DAC 5V can provide at least 3A.

  • Hi JIm,

    Have tried with 16dBm, 16.5dBm and 17dBm and see no difference. 

    I use 5A bench power supply. Thank you.

  • Do you have a TSW14J56EVM you can use to verify the DAC EVM is working properly?

  • Hi Jim,

    I've got a TSW14J56EVM tried with DAC38RF80EVM.

    outputs are fine although both SERDES PLL0/1 Out of Lock LED are also ON (not locked).