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ADS131M08: Register inquiry

Art Mecina
Genius 16505 points
Part Number: ADS131M08

Hello Guys,

Good day.

Our customer is using the ADS131M08 with an Xmega processor which is using 8 bit SPI. He selected the proper mode.
After the reset procedure he send a null command, followed by a dummy crc and 8 channel read out.
The status FF2800 is returned. So that seems ok.
As he understand it, he first send a command which is 3 bytes. first the MSB, then LSB and then a padding byte with 0.
After that the dummy CRC which are just 3 zero bytes, and then 8 channels which are 24 bytes with 0 value.
he got this :
00FF2800
000005BC
0005FF00
0000054E
etc.
the first byte is because internal he use dword. The null command (in total 10x3=30 nul bytes) should give the status register content which is 0500h.
But he gets : 0005FF00. What is this FF. He is expecting to get 0500xx

Can he assume that all registers have the reset value after a reset procedure?

Thanks in advance!

Art

  • 0
    TI__Guru 57306 points

    Hello Art,

    Thank you for your post.

    The input CRC is disabled by default. The customer does not need to send a dummy 24-bit CRC word after the first command word. Simply complete the frame the NULL command plus 8x 24-bit zeros. In the next frame, DOUT will contain the response to the first NULL command, which will be the STATUS register contents. After the reset procedure, the device will be restored to its default register values. The STATUS register should return 0500h. 

    Regards,

  • 0 in reply to Ryan Andrews
    TI__Genius 16505 points

    Hello Ryan,

    Thanks for looking into this. 

    According to the customer, the number of words in a command depends on the command provided. For most commands, there are ten words in a frame. On DIN, the host provides the command, the command CRC if input CRC is enabled or a word of zeros if input CRC is disabled, and eight additional words of zeros. So this tells him that CRC is not optional but that he need to send 0.

    He tried some simple code to see if he could determine the framelength :
    a - do a HW reset
    b - send x nul bytes and read back the result
    c - repeat this for 1 to 40 bytes
    At some stage he would expect a good result but the result is odd. See below:

    LOOPS: 1
    FF,
    LOOPS: 2
    FF,28,
    the loops say how many 0 bytes he send.
    then you see the result and as expected after 2 bytes he get FF28.
    But he cannot make sense of the other data.

    Let me know what your thoughts are.

    Art

  • 0 in reply to Art Mecina
    TI__Guru 57306 points

    Hi Art,

    You are correct about the input CRC, apologies for my confusion. I was thinking of another device for which the CRC is appended to the end of the frame. On the ADS131M08, the input CRC immediately follows the command word and precedes the channel data. When input CRC is disabled, please replace the CRC word with zeros as mentioned in the device data sheet.

    The RESET command requires a full frame for the reset to be latched. For the ADS131M08, this means a complete frame of 10x 24-bit words (30 bytes).

    Since the customer is using the /SYNC/RESET pin to reset the device, the only requirement is to wait tREGACQ (5 us) after the pulse rising edge before sending additional communication frames. This allows the device registers to return to their default state. 

    For now, please keep the frame size fixed to 30 bytes.

    Best regards,

  • 0 in reply to Ryan Andrews
    TI__Genius 16505 points

    Hello Ryan,

    Additional info and query from the customer. When he did a HW reset he always get the FF28 which is ok. But when he do a SW reset he do not get the FF28. He should get this on the next frame right? With HW reset you get it on the first frame.

    He also notice this in the sample code :

    /* (REQUIRED) Configure MODE register settings
    * NOTE: This function call is required here for this particular code implementation to work.
    * This function will enforce the MODE register settings as selected in the 'ads131m0x.h' header file.
    */

    writeSingleRegister(MODE_ADDRESS, MODE_DEFAULT);


    But according to him, why would it be required? This is the default after reset, so why would one send this default info?

    Can he count on the fact that all registers have their default value after reset right?

    Thanks!

    Art

  • 0 in reply to Art Mecina
    TI__Guru 57306 points

    Hi Art,

    The RESET command requires the full 10-word frame in order to be latched. Is the customer doing this? The response 0xFF28 will be contained in the first word of the following frame, as you mentioned. If the command word is recognized, but the frame is not completed, the RESET will not be latched and the response will be 0x0011h in the next frame.

    Let me get back to you on the reason for the "writeSingleRegister" command. This may be a redundant action to ensure the firmware has a correct record of the current device settings.

    Regards,

  • 0 in reply to Ryan Andrews
    TI__Genius 16505 points

    Thanks Ryan!

    For the meantime I will relay the information you provided to the customer.

    Art

  • 0 in reply to Ryan Andrews
    TI__Genius 16505 points

    Hello Ryan,

    Any update regarding the  "writeSingleRegister" command?

    Thanks!

    Art

  • 0 in reply to Art Mecina
    TI__Guru 57306 points

    Hi Art,

    Thanks for the reminder. I did check with my team and confirmed that this WREG function call is not required. In our EVM firmware, we've architected the code such that you can redefine the ADC startup configuration on power-up by changing the default definitions in "ads131m0x.h".

    Other sections of the code are dependent on the MODE register setting (i.e. the expected SPI word size). The user can make these changes to the header files and recompile the code to use the device in the mode they wish to evaluate. 

    Regards,