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Part Number: DAC38RF82EVM
I have some questions about SERDES/JESD crossbar.
There are description about Single or Dual Link Config on page 48 of the datasheet.
1. Was it the right configuration if like to used RX[4:7] for both DAC A/B, see attached.
2. Was it OK if seeing Lane[0:3] LOS message from Alarm Monitoring Window?
What LMFS setting do you plan on using? Do you want to operate with one slice or two? What physical pins will you be using for the DAC? Of these pins, which one will be lane 0, which one will be lane 1, which one will be lane 2 and which one will be lane 3 per the data coming from the FPGA? This will determine how the crossbar is setup.
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In reply to jim s:
1. The mode can be 84111 (primary) or 42111(secondary).
2. like to use DAC RX[4:7] pins for both DAC A and B.
3. FPGA lane[0:3] to DAC RX[4:7] pins respectively.
In reply to new2day:
You cannot use 42111 with two DAC's. This must be 4421. For your settings, the crossbar would look as shown below.
File attached in case graphic did not go through.
I guess I didn't make my self clear, sorry.
Actually, I like to run the DAC in 84111 mode Primarily and use DAC RX[4:7] pins only for both DAC A and B.
DAC RX[3:0] pins are not used.
Which means both DAC get same data from FPGA on RX[4:7] pins only.
1. Was it supported by this DAC? If yes,
2. How to configure the crossbar.
With LMFS = 84111, L = 8. L is the number of lanes. You will have to use RX[0:7]. I think you want to operate with only 4 lanes correct? Then you would use 4421 mode.
You could use 4421 mode, and send the same data from two of the lanes to the other two lanes..
See attached from the GUI at LMFS = 84111, both DAC or slices get same data from SERDES lane[3:0].
It make sense according to Table 12 of the datasheet. RX[3:0] carry DAC A samples while RX[7:4] carry DAC B data.
Was it right?
1. Can I used RX[7:4] for both DAC or slices instead? (LMFS = 84111)
2. It says in the datasheet it can be Dual DAC, single link. Was this true to all DUAL DAC configuration? Such as LMFS = 84111?
3. How to configure the Lane to use RX[7:4] only.
In case of LMFS = 42111 mode, would it be possible to send the data from FPGA onto DAC RX[7:4] Pins but not RX[3:0]?
Tell me exactly how many lanes you want to use, how many DAC's, and if the two DAC's are going to use the same data, IQ data or real, which pins you want to use on the DAC and how they map to the FPGA and I will come up with a configuration for you. 4211 is only for single DAC mode. See table 9 of data sheet.
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