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DAC80004: Spice model for running simulation in virtuoso

Prodigy 70 points

Replies: 14

Views: 151

Part Number: DAC80004

Hi,

I need the spice model(.CIR file) for DAC80004IPW. The one which is available on ti.com is the encrypted model. I need the unencrypted one, as i want to create a symbol for  this component and then use it in a test bench. 

  • Hi Avi,

    I am not sure if we have an un-encrypted version of the TINA sim.  I will check within the team.

    Thanks,
    Paul

  • In reply to Paul_Frost:

    Hi Avi,

    Please find the unencrypted spice model for DAC80004.

    Note we have verified this model with TINA-TI and Pspice. You may encounter some syntax related errors when you are importing this model into Cadence Virtuoso. You need to correct the error, if you get the same. I am not familiar with Cadence Virtuoso syntax when you are importing models compatible with TINA and Pspice.

    Regards,

    AK

    DAC80004.cir

  • In reply to Akhilesh K:

    Hi,

    Thanks for the .CIR file. I imported the .cir file to Virtuoso in Pspice view. I have a doubt regarding the pin configuration. I have attached images of the symbol that I got using the .cir file in virtuoso and the image of the device in the data sheet. Some pins in the symbol are different from those in the datasheet. Could you help me out with this.

  • In reply to Avi Singhal1:

    Hi,

    Please see the symbol from TINA. SEL A to D is used for which channel is selected for outputs. That is just for simulation purpose. example below shows cap load drive test for Ch A with SEL A tied to high.

  • In reply to Akhilesh K:

    Hi Akhilesh!

    Which pin is the CLK in this setup?

  • In reply to Vinay Shekhar:

    Hi,

    This simulation model is asynchronous and the data bits are loaded directly without any clock edge.

    Regards,

    AK

  • In reply to Akhilesh K:

    Hi,

    Is it possible to get a synchronous model for DAC80004? or the synchronous model for some other DAC in the same series.

    Regards

    Avi 

  • In reply to Avi Singhal1:

    Hi,

    All our spice models for DAC are asynchronous, since the goal of the models is to simulate the output behavior like cap load, stability, current drive, noise etc.

    One device series which has this serial clock modelled is DAC8311, but that model is encrypted

    Hope you understand.

    Regards,

    AK

  • In reply to Akhilesh K:

    Hi,

    I tried importing the .CIR file for the model that was provided to virtuoso in pspice view, and created the test bench. While simulating i am getting an error, it says that the mapping is not proper. I have attached the screenshot of the error and the lines to which the error is pointing. Kindly advise.

  • In reply to Avi Singhal1:

    Hi,

    Attachment is missing. If you want to attach any picture, please use the picture tool from the edit box and upload the same.

    As such I am not an expert in Virtuoso, but still I can look into the error, if you post the picture.

    Regards,

    AK