ADS1274: Operating with IOVDD at 1.8V

Hi Robert,

Welcome to the TI E2E Community!

The ADS1274 should have equal performance over the IOVDD operating range.  A couple of thoughts.

1.  Is the IOVDD supply noise when using 1.8V similar to 3.3V?  If the noise is much higher, this could explain a difference in measurement noise.

2.  The main CLK input is also referred to the IOVDD supply.  Is this clock powered from IOVDD?  Is it rated to operate at 1.8V?

3.  Also, with respect to the clock, are you getting the correct voltage levels at the CLK input pin when operating at 1.8V?  

Regards,
Keith Nicholas
Precision ADC Applications

Thanks for the input.

IOVDD supply is the same buck-boost converter used at 3.3v running at similar current but lower voltage. So noise could be higher but not enough for my equipment to see. I tested by substituting a bench supply for DVDD/IOVDD (switched together manually prior to AVDD) and there is no change.

The main clock is powered from the same supply but they are switched independently. Clock comes from a microcontroller running at 1.8V.

Clock and all other signals look clean going into the board which is 2" dia.

Looking at the SPI data on a scope it looks good except there seems to be about 12 bits of noise.

I forgot to mention, but the data is going to an FFT to produce a 128 bin spectrum over 128 Hz. The noise is flat, no spikes indicating a signal leaking in.

Placing a waveform generator on the analog buffer input gives strange results. As the input signal amplitude is reduced the FFT signal suddenly disappears before it has dropped to the level of the noise. With the amplitude set to show a signal well above the noise, the FFT will sometimes change amplitude suddenly, by about a factor of 2. It is the same software and hardware that works correctly at 3.3V, so it seems like an issue in hardware.

The input buffers are the same THS4524 used in the reference design. Negative is tied to 2.5V. I verified that the input from the analog buffers to the ADS1274 show about 2.5V to + and - input at 2.5V input. As the input amplitude changes, noise levels remain the same.

Robert Watson
Next State Corporation
rwatson@nextstatecorp.com
Mobile: 325-668-7598

Hi Robert,

I have seen noise issues when reducing the IO voltage to 1.8V, but in all cases, it has been due to the clock source not working to spec, with a much higher jitter.

Do you have a good oscilloscope or other instrument that you can use to measure the clock jitter from your MCU, both at 1.8V and 3.3V?  Right now, that is my best guess as to why you see much higher noise.

Regards,
Keith

Thanks Keith

The best I have been able to do with the digital scope is 500uSec/div and it shows no jitter.  A counter measuring the clock period with a resolution of 1 nSec shows no jitter. This is at 1.8V. I didn't measure the 3.3V system since I couldn't measure anything better.

The 1.8V power supplies are 1.8V. The 1.8V signals are 0V and 1.8V with three exceptions.

With DVDD and IOVDD on, AVDD off, the main clock is -100 mV low, 1.9V high. With AVDD on, the clock high level is 2V, DOUT[0] high level is 2V, DRDY swings from -150mV to 1.9V.

Possibly the negative level on the clock could be a problem? I'll check the levels on the 3.3V system, but the signals are not easy to access.

Robert Watson
Next State Corporation
rwatson@nextstatecorp.com
Mobile: 325-668-7598

Jitter at 1.8V is 3.5 nSec. At 3.3V it is 3 nSec. This is at the limit of my oscilloscope.

At 3.3V, the signal offsets were similar. CLK is still -100 mV when low. Probably not the problem.

Hi Robert,

I am not certain of the root cause, but it is likely to do with the CLK pin when operating at 1.8V.

Do you have an external clock source that you can use for the CLK pin and check operation?  SCLK and CLK will not be synchronized in this case, and the noise will be degraded, but not to the extent that you observe.

Regards,
Keith

Keith,

I used a waveform generator with a jitter specification of less than 40 ps I measured less than 2 ns, probably the best the oscilloscope can do.

There was no change.

Thanks

Hi Robert,

We were able to dig up some data for the ADS1274 measuring noise verses IOVDD, with IOVDD adjusted from 1.65V to 3.6V.  There is a very small change in noise as IOVDD is adjusted, but on the order of a few percent, not 1000x.

The only other parameter that I can think would change are the timing delays which typically increase at lower voltages.  Could you provide a timing diagram for the SPI?  DOUT, SCLK, and CLK?

Also, I read through the information you provided again.  Is there a possibility that the CLK, or other IO lines are driven before IOVDD is settled?  If so, this could cause the device to not operate properly.  After power-up, please assert the /SYNC pin, which will have the effect of resetting the device.  If there are any issues during power-up, this should fix it.  

Regards,
Keith

Thanks for looking into that Keith.

In the 1.8V system DVDD and IOVDD are tied together and switch on together. I have confirmed that AVDD switches on afterward. I have checked all digital signals input and they are logic 0 until the ADC has powered up. I don't recall the delay but it was significant.  Analog signals are powered by the same +5V on the same switch as AVDD and would be powered up at the same time as AVDD. When I began having trouble I added a toggle for the SYNC pin for the reason you suggest but it didn't change anything.

I don't have a logic analyzer to place on the SPI port and my oscilloscope can only display 2 channels at one time. I can take a picture of the display with DOUT and SCLK.

CLK and SCLK are derived from the same oscillator but their frequencies are not a simple multiple. The controller chip I am using just was not able to create the SCLK frequency needed and the CLK had to be such that the FFT produced bins at integer frequency intervals. This worked well at 3.3V so I wasn't expecting it to cause a problem at 1.8.  I'll see what SCLK choices I do have.

I will double check the digital signals again to ensure none have a signal until well after AVDD on.

Thank you,

Robert

Hi Robert,

Let's check the timing between the SCLK falling launch edge and DOUT, t-DOPD.  Decreasing the IOVDD voltage increases the maximum propagation delay time from 26nS to 32nS.  You may be missing the correct data in this case.  If your MCU is capturing data on the rising edge of SCLK, in order to meet the t-DOPD value of 32nS, your maximum SCLK frequency should be no more than about 12.5MHz.

What is the frequency of CLK and SCLK?  If there is a timing issue, try slowing SCLK down by 50% (assuming you can still clock all 24b data within the data rate period).

Regards,
Keith

Keith,

CLK is 131,072 Hz

SCLK is 655,364 Hz.

Ratio is 5.00003 to 1.

The SPI controller is sampling on the rising edge and the oscilloscope shows this to be in the middle of the data valid region as expected at this speed.

I have put a DC input to the buffers to bias them to mid-range (near 0 on the A/D output) and looked at the data on the oscilloscope to confirm the SPI data. The first 11 bits are constant (0000 0011 100 in the latest test) with the next 13 bits noisy. This is similar to the noise the controller is reading.

Thanks again

Hi Robert,

I am not sure if this is causing the issue, but SCLK cannot be greater than CLK frequency, even at lower frequencies.

Please reduce SCLK to 131072Hz or less and see if the part works correctly.

Regards,
Keith

Keith,

I was particularly hopeful on this one. I've read that part of the data sheet countless times and read it wrong every time.

CLK is now 524,288 Hz

SCLK is 327,682 Hz

No change.

Thanks again.

Hi Robert,

Can you confirm that this behavior occurs on more than 1 board, or more than 1 ADS1274 device?

Regards,
Keith

Keith,

Yes, several. I just tried another new board and the result is the same.

It's looking to me as if there is something in the 1.8V layout that I can't pick up on the oscilloscope.

Robert

Hi Robert,

Summary of tests that did not fix the problem:

1.  Powered IOVDD using a bench supply verses board switching supply.

2.  Provided an external clock source from a waveform generator.

3.  Verified same issue on multiple boards.

4.  Verified all supply voltages are within recommended operating range.

5.  Checked timing requirements are being met between SCLK and DOUT.

6.  Verified t-DS, delay between DRDY falling edge and rising edge of first SCLK, 1 t-CLK period.

7.  Reset the device after power-up by asserting SYNC.

8.  Verified no digital or analog inputs are driven at a higher voltage than the supply voltages during and after power-up.

If I can think of any other tests, I will let you know.

Regards,

Keith

Keith,

A few more that might need to be on the list.

9. Powered AVDD from a bench power supply.

10. Powered IOVDD after DVDD.

11. Verified AVDD powered after IOVDD.

12. Corrected SCLK to be less than CLK

13. Disconnected analog buffer and tied AINP/AINN to +2.5v

Thanks, Robert

Hi Robert,

I do not have any more suggestions at this time.  If I think of something else to try, I will reply to this thread.

Regards,
Keith

Thanks Keith, for now we'll switch back 3.3V.

Robert Watson
Next State Corporation
rwatson@nextstatecorp.com
Mobile: 325-668-7598

Understood.