ADS1256: ADS1256 Reset issue

Hi Brian,

Can you please help explain what occurs before the calibration values change? Is there a pattern to this issue, or is it random?

When you say the device has reset, have you checked the other registers to see if they have returned to their default values? Or have only the calibration registers changed?

Have you monitored the SCLK line to see if the reset pattern occurs at any point? The SCLK reset does not reset the CK0 and CK1 bits in the ADCON register, while the hardware RESET does, so this would be a good indication that a reset occurs as well as which reset has occurred (if at all).

Please let me know so we can help identify what is going on here.

-Bryan

The issue is random and has been difficult to reproduce.  I am seeing ~2% reduction in the values reported by the ADC, yet the input voltages and VREF have not changed.  I am able to simulate the behavior I see by externally pulsing the reset line.  This leads me to suspect that the ~2% reduction is caused by the ADC unexpectedly resetting during operation which causes a selfcal at the default data rate instead of the data rate we are using.  I have temporarily remedied the situation by checking the Full Scale Calibration(FSC) value after each measurement to determine if the ADC has been reset.  If I detect that the FSC has changed, I initialize/calibrate the ADC and resume operation.  This is an adequate temporary solution, but it would be better if I could determine what is causing the reset and prevent it from happening.  What are recommended capacitor values for Avdd, and Dvdd?  Do you recommend any capacitors/pull-ups/RC circuits on the reset line?  Is it recommended to disconnect the SCLK line to prevent communication with other devices on the SCLK from triggering a reset?  As mentioned, the issue is random and hard to reproduce, so I don't have any evidence as to what is actually causing the reset.

Hi Brian,

Have you checked the other registers when this issue occurs to see if a full RESET actually happened? It would be good to confirm that a reset does occur (and that it is not just affecting the FSC registers), as well as the type of reset that it is. As I mentioned in my previous post, the D1 / D0 bits do not change during an SCLK reset, but would revert back to default if the RESET pin was toggled. I would recommend that you include a register readback after you perform the FSC register check. It would also be helpful if you had a logic analyzer shot of the digital communication lines both before and after the error.

The recommended bulk capacitors for the supply pins are shown in Figure 25 in the ADS1256 datasheet (10uF in parallel with a 0.1uF).

You can put a pull-down resistor to DGND on the SCLK line to keep the line low while not being actively driven.

You can put a pull-up to DVDD on RESET to keep this pin high while not being actively driven.

Let me know if you have any feedback on my initial questions, or if you can get the logic analyzer images.

-Bryan

The register values and logic analyzer screen shots would be extremely helpful.  Unfortunately as I mentioned in my previous post, the problem is random, and I have had no success in reproducing the error making gathering the info you request logistically challenging at this point in time.  I will look into implementing the circuit changes to see resolves the issue.

Hi Brian,

Can you send me your schematic and register settings? Perhaps there is an issue there that I can help identify.

And when the FSC values are changed, are they reset to defaults or just some other value than what you intended?

-Bryan