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ADS54J60EVM: Synchronize JESD204B multi-board system

Daniele Buono
Prodigy 30 points
Part Number: ADS54J60EVM
Other Parts Discussed in Thread: LMK04828

Dear Srs.

I'm trying to build up an acquisition system for phased array application. The system architecture is composed by 2 ADS54J60EVM boards (Dual-Channel, 16-Bit, 1.0-GSPS), each connected to a different FPGA carrier board.

I've already read that a synchronization between the 2 subsystems is possible using a common, 10MHz reference input signal (with matched cables length) fed to LMK04828 devices, as to generate synchronous and phase matched sample clocks and SYSREFs. It is correct?

Once implemented this scheme, how it's possible to merge data acquired from the 2 different subsystems? How can I synchronize JESD204B frames from the different FPGA boards?

Thanks in advance for the availability 

Best Regars

  • 0
    TI__Guru* 91947 points

    Regars,

    For your first question, the answer is yes. This can also be done using the LMK in single PLL mode with a higher reference frequency. See attached. 

    For your second question, this should be possible by creating an AND of the SYNCn signals from the two FPGA IPs and connecting that to the two ADCs. This assumes that all devices are correctly synchronized using SYSREF, and there is a common clock being fed to the two EVM’s.

    Regards,

    Jim

    7080.Dual LMK04828 CLOCKING SETUP.pptx

  • 0 in reply to jim s
    Prodigy 30 points

    Jim,

    Many thanks for your answer.

    I've summarized the connections in the diagram attached below. The idea is to force a synchronization in both ADCs forcing simultaneously the output SYNC signal to both JESD transmitters, it's correct?

    Alternatively, it's possible to do this sending a simultaneous request to both FPGA JESD cores through a dedicated core input ?

    Regards,

    Daniele

    ADC_Synchronization.pptx

  • 0 in reply to Daniele Buono
    TI__Guru* 91947 points

    Daniele,

    Why is the output of the AND gate going back to the FPGA IP core? This does not appear correct. The AND gate output should be the SYNC going to the ADC. Otherwise your drawing appears correct.

    Also the SYNC should be sampled by both ADC's in the same LMFC period. See diagram attached from JESD204B standard.

    Regards,

    Jim

    Clocking Scheme - Subclass 1.pptx

  • 0 in reply to jim s
    Prodigy 30 points

    Jim,

    you're right, the diagram was not clear about the direction of that signal, my intention was to force the output SYNC' signal with both AND gate output and JESD core SYNC output.

    In this way a synchronization procedure can be triggered by both an external source (TRIGGER_1/2) and JESD receiver core itself. Below attached the correct diagram.

    Is this approach correct?

    Many thanks for your answers and your availability

    Regards,

    Daniele

    ADC_Synchronization_v2.pptx

  • 0 in reply to Daniele Buono
    TI__Guru* 91947 points

    Daniele,

    If the symbol you show as a mux is really an AND gate like the one that has the trigger inputs, this looks correct. If you want both ADC's to be synchronized and have deterministic latency, it is critical the trace lengths of the SYSREF and device clock going to both ADC's is the same length from the clock source. Same for the SYSREF and device clock going to both FPGA's. Also the SYNC must be received by both ADC's within the same LMFC period.

    Regards,

    Jim