Other Parts Discussed in Thread: CDCE6214
To achieve coherent sampling with a delta-sigma adc at high sample rates, the only option is to tune the clock itself. For instance if nominal sampling speed is 128000 SPS with +- 10% range, this could be achieved by 32.768 kHz +-10% clock. Problem is to generate such clock in a flexible and affordable way.
What are your suggestions?
/Peter