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ADS1278: Flexible clock generation

Part Number: ADS1278
Other Parts Discussed in Thread: CDCE6214

To achieve coherent sampling with a delta-sigma adc at high sample rates, the only option is to tune the clock itself. For instance if nominal sampling speed is 128000 SPS with +- 10% range, this could be achieved by 32.768 kHz +-10% clock. Problem is to generate such clock in a flexible and affordable way.

What are your suggestions?

/Peter

  • Hello Peter,

    Welcome to the TI E2E Community!

    The output data rate for the ADS1278 in high speed mode is Fclk/256.  As you pointed out, you can adjust the data rate to an exact frequency by adjusting the CLK input frequency.

    There are many clock generator options that could be used.  For the evaluation board, we use the PLL clock resource inside the DSP.  Taking a quick look, something like the CDCE6214 should be a very good option, but I am not an expert with these devices.  In any case, a total clock jitter of 10pS-rms or lower will work well.

    I suggest you submit another E2E post if you have specific questions regarding the CDCE6214 or one of the many other clock generator options.

    Thanks!

    Keith Nicholas
    Precision ADC Applications