TSW1400EVM Source Code?

HI KH,

can i get the verilog codes of TSW1400 connected with DAC3152 and TSW1400 connected with ADS4229?

thanks a lot

-yzj

Hi YZJ,

The example project copied above is a great starting point for the ADS4229 and the DAC3152. For the ADC side, the only change needed is changing from a 14-bit interface to 12-bits. For the DAC side you'll need to change to a 10-bit interface but the majority is the same. The DAC does not have a source-sychronous data clock, so you'll need to play with the timing to get it right. You might also want to consider the DAC3154, which does have a source-synchronous data clock.

Regards,
Matt Guibord 

thank for your answers.

If i connect ADS4229EVM and DAC3152EVM to TSW1400EVM，on the ADS4229EVM，shoud i set the data formate 2‘s complement LVDS or the Bin LVDS？

Dose DAC3152EVM recognize the 2‘s complement LVDS or the Bin LVDS？

thanks a lot.

Hi YZ,

The DAC3152 expects offset binary data. This is indicated in the description for the IOUTAP pin on page 2 of the datasheet.

Regards,
Matt Guibord 

thanks for your answers

i connect ADS4229EVM and DAC3152EVM to TSW1400EVM，on the ADS4229EVM if i setup the code formate 2's complement,transform it to offset binary in my verilog codes;but i setup  the code formate offset binary ,use the same verilog codes,it turn out the same result.

i want to answer:i want to setup the code formate for the ADS4229,can i only finish it by the JP14 on the ADS4229EVM? if not ,what should  i do?

regards

Hi YZ,

Yes, JP14 can be used to set the data format. In order for it to work, the ADC needs to be configured for parallel programming. This is done by making sure the jumpers for JP8, JP9, JP10, and JP11 are between pins 1 and 2.

Regards,
Matt Guibord 

Greetings,

Is it possible to get a copy of the FPGA Verilog source used on the TSW1400 when connected to a ADS5403 Evaluation board.  We are trying to understand the bandwidth of the FPGA to USB data bath.

Thanks.

Mike Shea

Hi,

The Verilog source code for the TSW1400 has been written in such a way that much of the code that is common has been compartmentalized away from the code that is specific to each ADC format, and a few set of parameters in one place in the code would be set for a specific ADC family and the bit file generated.  Then those parameters would be set for another ADC family and the bit file generated.  So by the time we are done, we don't have the source code sitting there for a specific device like ADS5403 unless that was the last ADC that we generated a bit file for.  it's nice for upgrades to the TSW1400 having to support so many different EVMs - not so nice when someone asks for code specific to a device.

Most code requests have to do with how to impement an ADC to FPGA interface for a specific device, and that is why Matt has created one app note for the TSW1400/ADS4249 combination.  Other app notes are to follow for other ADC/TSW1400 combinations.   I *do* have an example code base that closes timing for ADS540x into the StratixIV that Altera generated specific to this ADC.

But it sounds like you are not interested in the ADC interface, but rather the unloading of the data through the USB port, correct?  I don't know if the Verilog source will tell the whole story there.  There is also a C-code dll on the PC side that greatly influences the speed of the USB transfer.

I'll tell you what I know of the unloading of the data from the FPGA to the USB and then let us see what you still want to see after that, if that's ok.

The USB chip on the TSW1400 is a four port device called the FT4232.  It has four bytes of general purpose IO that can be accessed from the USB side using the drivers from FT.  Each of these bytes of IO pins are a port, and two of the four ports have additional internal hardware to speed up serial access such as for 3-wire or 4-wire SPI ports.  On the TSW1400, we use one of the ports to emulate a JTAG port and push the bit file into the FPGA at run time.  We use another port to access a simple bank of registers in the FPGA for control purposes to set the FPGA up for a particular type of capture.  But the remaining two IO ports - the ones that can support a higher throughput - are used to move sample data out of the DDR2 memory stick through the FPGA and up to the PC.  These two SPI ports out of the FPGA to the USB chip are used in tandem to double the transfer rate than we would get if we used only one SPI port.  Half the sample is moved out on one SPI port, and half the sample is moved out on the other SPI port.  I believe the max rate of each SPI port is 25MHz.  That would set the max rate of moving data out of the FPGA.  The limiting factor seems to be on the PC side, in how fast the PC can accept data.    What version release of the HSDC Pro GUI are you using?  I think we just released version 2.2, and the effective transfer rate from the TSW1400 to the PC is greatly improved without changing the architecture of using 2 SPI ports i just described at all, so depending on what it is you are wanting to see or do would determine if we want to continue talking about the DLL on the PC side, the use of the 4-port USB chip, or really look at the firmware code of the FPGA.  (And the bandwidth of the FPGA to USB data path is not in any way tied to the use of an ADS5403 or any other ADC, really.  The choice of ADC influences how fast the data fills up into the memory, not how fast the USB can unload it.)

Regards,

Richard P.

Regards,

Richard P.

Greetings Richard,

Thank you for the reply. 

I asked for the FPGA Verilog code so I could see how sample data is transferred between the FPGA and USB chip.  I wanted to estimate the throughput of the transfer. 

Your very thorough response completely answered my questions.  At this time, I have what I need so you don’t have to send me the code.

Thanks again,

Mike Shea

Hello Kang Hsia,

Thank you for this post. I just wanted to download the app-note and Altera project for TSW1400 however the links do not work any more..

Could you please help out with this and provide working links?

Thank you,
Marcinski

Hi Marcinski,

We're in the process of transitioning the document into a new format, which seems to have broken the links. I've sent a request to get this fixed. If this cannot be fixed in a timely manner I will e-mail you the files directly.

Regards,
Matt Guibord 

Hi Matt,
Many thanks for the help. I would really appreciate it.

Regards,
Marcinski

Hi Matt,

I myself tried to download the code but it doesn't exist there.

Can you also email me.

matlab_fft@yahoo.com

Thanks.

-BAS

The link should be fixed by midday tomorrow after the servers update. Please try to download the documents then. I'm sorry for the inconvenience.

Regards,
Matt Guibord 

Many thanks Matt.

I does work again!

I have to send 150bits for another board from TSW1400evm (via SPI). I already built a Verilog code to do that and test it on Altera DE-2. Now I need to implement this code on FPGA from TSW1400. I think that I will need change the original code to allow my module to access the data that I will send from my computer to some register and then send those 150 bits out.

Could you send me the Verilog code of TSW1400?

My email is danilo_jcamara@yahoo.com.br

 Thanks

Danilo

Hi Richard -

You mentioned (above) having Altera FPGA code for ADS540x . Is this a project with the ADC interface in HDL and the necessary timing constraints? If so, I would be very interested in getting a copy of the project if possible?

Thanks,
Charlie

Charlie,

You can download the firmware from the following link:

https://txn.box.com/s/srnzy7mx0ft1osws7hluqdozeholbsxu

Regards,

Jim