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[ADC08D1520RB] - Verilog testbench

Evripidis Karseras
Intellectual 735 points

Other Parts Discussed in Thread: LMX2541

Dear Support,

Here I am to bother you again. This is an easy one though.

1) From what I understand from the verilog code; the PLL's registers are programmed via the FPGA with hard-coded values. The command though to begin programming the PLL comes from WV5 and lies in the corresponding XML-like script. Is this correct (this question was answered a while ago, just checking ) ?

2) The FPGA deals with programming the ADC with values from the script ? I believe this is the case as well ?

3) Is there a testbench for the top-level verilog module that you can provide ?

4) I noticed that communication with the PLL is done via a module called "lmk_spi". Obviously it is working fine and needs not messing around with. My question is; was this module coded by you guys ? I know there is IP provided by Xilinx for SPI, why was not this used ? Is there a particularity involved I should be aware ?

Thanks in advance and waiting patiently for your responses.

-E

  • 0
    TI__Mastermind 44680 points

    Hi Evripidis

    In answer to your latest questions:

    1) Yes, this is correct. This section of the script is used to initiate the sequence:

    <combo_box
                    id="clk_sel"
                    count="2"
                    selected="0"
                    caption="Clock Selection (Board relay U1)"
                    hint=""
                    units=""
                    highlighted="false"
                    enabled="true">

                    <item id="Internal Clock" value="0"/>
                    <item id="External Clock" value="1"/>

                    <actions>
                        <action_set_reg_bitfields reg="opt1" pll_disable="settings:clk_sel:value"/>
                        <action_exec_seq seq="mm_wr" cmd:addr="opt1:addr" cmd:reg_val="opt1:all" />

              <!-- program PLL based on FPGA code - RB -->
                    <!-- Note that the LMX2541 cannot be programmed with XML script method due to LE pulse width requirement.
                         There is an FPGA module with the register values hardcoded activated by
                         transitioning pllprog from low to high. -RB -->
                        <action_set_reg_bitfields reg="opt1" pllprog="0"/>
                        <action_exec_seq seq="mm_wr" cmd:addr="opt1:addr" cmd:reg_val="opt1:all" />
                        <action_set_reg_bitfields reg="opt1" pllprog="1"/>
                        <action_exec_seq seq="mm_wr" cmd:addr="opt1:addr" cmd:reg_val="opt1:all" />
                        <action_exec_seq seq="wait" cmd:ms="50"/>     

                        <action_set_reg_bitfields reg="opt2" ext_clk_sel="settings:clk_sel:value"/>
                            <action_exec_seq seq="mm_wr" cmd:addr="opt2:addr" cmd:reg_val="opt2:all" />
                        </actions>

              </combo_box>

    2)  Yes, the updated register values from the script are sent to the ADC via the FPGA SPI write module.

    3) Unfortunately, no there is not.

    4) I'm not sure who wrote the PLL write module code. I will see if I can find out who did it, and why it was needed. In my experience, some device serial interfaces are slightly different than the standard SPI or Microwire protocols implemented by the FPGA vendors. This may have been the case here. To understand this would require comparing the detailed SPI timing specified for the Xilinx IP with the serial interface details for the LMX2481 device.

    I hope this is helpful. Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Intellectual 735 points

    Hello Jim,

    Thanks for your replies and information. 

    What you say in (4) is correct and I cannot think of any other reason. Maybe a testbench would have been helpful for this case as well. In any case, since it works....

    Thanks again.

    -E.