ADC08D500 Output Data Bus

Hi Dan

I would like to understand why they are interested in doing this. What benefit do they plan to achieve by doubling the number of converters? How many analog inputs are being sampled in the current plan, and how many would be sampled in the new scenario? What is the desired signal sampling rate in each scenario?

If 1 GSPS is the desired sample rate for each analog input, then the best solution for performance and minimum output data lanes is the ADC08D1020 operating in non-demux output data mode. In this mode each input is sampled at 1 GSPS and the data bus of each I or Q channel is 8-pairs at 1 Gbit/sec with DDC clocking (DCLK at 500 MHz).

To address the specific questions:

First question: The ADC08D500 converter data outputs always operate in 1:2 demux mode, with 16 pairs of data per each I or Q channel. In two channel mode it does not support the 16-bit data bus mode.  The only way to get 16 bit output is to power down the Q channel and operate the device as a single, roughly equivalent to the ADC08500 device.

Second question: The ADC08D500 does support Dual Edge Sampling (DES) mode and can sample one input (VINI +/- for example) with both the I and Q internal converters. The I-converter will sample the input on the rising edge of the input clock and the Q-converter will sample the input on the falling edge of the input clock. The effective sample rate in this mode is 1 GSPS. The output data will be presented on all 32 output pairs.

In non-DES mode both converters sample their respective inputs on the same edge of the input clock.  the I-input is only sampled by the I-converter and the Q-input is only sampled by the Q-converter. If no signal is present on the Q inputs then no useful data will be available on the DATAQ-outputs.

Best regards,

Jim B

Hi Jim,

Here's the responses back from my customer highlighted in Yellow.

I would like to understand why they are interested in doing this. What benefit do they plan to achieve by doubling the number of converters? 

>>> We are migrating from a three channel system to a six channel system. Thus six independent sampling channels at 500 MSPS.

  How many analog inputs are being sampled in the current plan, and how many would be sampled in the new scenario? What is the desired signal sampling rate in each scenario? 

>>> Three channels in the current system at 1 GSPS (ADC08D1520), note each ADC uses 8 pairs x4 data lines on the output. Six channels in the new system at 500 MSPS (ADC08500), note each ADC would use 8 pairs x2 data lines on the output. The data lines feed into an FPGA. The thought was to use the same FPGA for both the three and six channel system, as they would have the same number of data lines.

If 1 GSPS is the desired sample rate for each analog input, then the best solution for performance and minimum output data lanes is the ADC08D1020 operating in non-demux output data mode. In this mode each input is sampled at 1 GSPS and the data bus of each I or Q channel is 8-pairs at 1 Gbit/sec with DDC clocking (DCLK at 500 MHz). 

>>> Our current system uses the ADC08D1520 at 1 GSPS. Since all of these ADCs have the same footprint, we wanted to test with a slower ADC (500 MSPS) using 8pairs 2x data lines. One of our CCAs has installed on it 3 channels of ADC08D500, so the thought was to reprogram the FPGA to utilize the 8pairs 2x data lines instead of the 8pairs 4x data lines 

To address the specific questions:

First question: The ADC08D500 converter data outputs always operate in 1:2 demux mode, with 16 pairs of data per each I or Q channel. In two channel mode it does not support the 16-bit data bus mode.  The only way to get 16 bit output is to power down the Q channel and operate the device as a single, roughly equivalent to the ADC08500 device. 

>>> We would want to power down the ADC08D500 Q channel in order to operate in 16 bit output mode equivalent to the ADC08500. This is for purposes of test, to program the FPGA to process 8pair 2x data line data instead of the 8pair 4x data line data.

Second question: The ADC08D500 does support Dual Edge Sampling (DES) mode and can sample one input (VINI +/- for example) with both the I and Q internal converters. The I-converter will sample the input on the rising edge of the input clock and the Q-converter will sample the input on the falling edge of the input clock. The effective sample rate in this mode is 1 GSPS. The output data will be presented on all 32 output pairs. 

>>> Understand, thanks. 

In non-DES mode both converters sample their respective inputs on the same edge of the input clock.  the I-input is only sampled by the I-converter and the Q-input is only sampled by the Q-converter. If no signal is present on the Q inputs then no useful data will be available on the DATAQ-outputs. 

>>> But the "no useful data" will still be pumped out on the DATAQ-outputs, correct? 

Hello TI,

Can you respond to the latest?

Thanks,

Dan

Hi Dan

To have the fewest number of output buses for a 6 input 500MSPS system, the best solution is to use 3x ADC08D1020 with the devices operating in non-demux output mode and with a 500 MHz clock. There will be six 8-bit output data buses. If they need to sample faster they can just increase the clock rate later. Unfortunately we don't have a pin compatible 500 MSPS part that can do the non-demux mode they need. If they use the ADC08D500 or ADC08D502 then there will be twelve 8-bit data buses.

To clarify the answer to the 'no useful data' question. If the ADC is operating in non-des mode with both I and Q channels active, those channels will convert whatever is present at the inputs. If channel I has an active signal at the input then that data will be converted and show up at the I channel data outputs. If the Q channel inputs are not driven and the signals are AC-coupled, then values near mid-scale will be output on the Q channel data outputs.

Best regards,

Jim B

Hi Jim,

Follow up question:

>>> What if I wanted a 6 input 1 GSPS? Would there be twelve 8-bit data buses? What would the output data bus clock rate need to be?

For 6 inputs at 1GSPS, the ADC08D1020 is the best solution.

With the ADC08D1020 (quantity of three devices), in 1:1 (non-demux), the output data will be at 1 Gbit/sec on six 8-bit LVDS buses. The DCLK will be operating at 500 MHz (DDC clocking).

If that data rate is too high, they could operate the devices in 1:2 demux mode at 500 Mbit/sec. This will be on twelve 8-bit buses. The DCLK can operate in either DDR mode at 250 MHz or SDR mode at 500 MHz.

Best regards,

Jim B