I have a board that uses an ADC16DX370 with a 325 MHz clock. I am using just one channel (A). The ADC is connected to a GTH transceiver of a Xilinx Kintex UltraScale FPGA.
Described in few words, the problems I observe is the following: when the analog signal level is low, the serial data transmission is perfect. However, when the analog signal level increases to about -27 dB FS, the GTH (SERDES) core reports very frequent line code errors which produce a resynchronisation (SYNCb assertion) of the ADC.
It follows the details:
- The analog input is DC coupled to a THS4509 differential driver through two serial 10R resistors and one 200R resistor in differential termination, in parallel to the input, forming a low attenuation voltage divider.The common mode voltage of the amplifier comes from the ADC. Values are inside specification, very close to nominal ones. There is low noise, however there was previous measurements that revealed low frequency noise. However, I could not repeat measurement, maybe due to poor probe grounding.
- The CLKIN comes for a IDT8T49N203 whose outout is configured for LVDS level. It is AC coupled with 2x100 nF capactitors. Clock frequency is 325 MHz.
- SYSREF comes from the FPGA through an FMC interface. The line is AC coupled and includes a termination resistor like figure 48 of ADC datasheet. The OM1 register has been configured to 0x85, as recommended. I make an initial synchronisation and then the gate is disabled.
- SYNCb is comes from the FPGA through direct connection to the ADC (as in figure 51 of the ADC datasheet)
- ADC serial data output is connected to a FPGA GTH input through 2x10 nF capacitors.
The serial differential pairs have been traced with great care in the PCB.
When the ADC sees a very small signal level (just noise) the operation is flawless. SYNCB synchronisation is done at the beggining and everything runs smoothly.
When I insert a tone whose level is about 0.046 of full scale (peak output codes about 730 and -2200) everything is also correct.
However, if I slightly increase (1 dB) the analog input level, the GTH transceiver in the FPGA reports errors in very frequenct bursts and the logic in the FPGA activate the SYNCb output in order to force reaquisition of the serial signal.
I have checked OVRA signal and does not activate. It does when the signal level is very high.
If I program JESD204B test patterns like JESD_TEST_MODES=7, everything runs flawlessly despite the level of the analog signal at the output. I have also tested ramp test with different steps sizes and the result is also perfect: no errors, no resyncs and perfect ramps.
While an slow ramp test (RSTEP=1) is running, I tried to program different deemphasis levels in order to check the serial link robustness. No errors were found in the line while VOD is 0 and DEM is configured to any value from 0 to 7.
While in normal mode operation with the highest level sinusoid that produces no errors, I changed the preemphasis configuration. When DEM is 0 to 5, no line code errors were detected. When DEM is configured to 6, very esporadic error bursts are detected and when DEM is configured to 7 there are bursts of errors. Sometimes the error is just a byte and does not activates SYNCb, sometimes are longer and the SYNCb reacquisition sequence is triggered.
I have been able to see that the SYNCb activation is allways a consecuence of a large burst of errors (and not the inverse order).
I have tested two boards, with the same result.
It seems to be an interaction between the an alog input level and the serial data output, but this is very unlikely.
While I continue investigating all comments are welcomed.
Best regards
Luis Migue
