ADS8354 timing diagram page 37 38

Ed Walker

Other Parts Discussed in Thread: ADS8354

Hello Precision Data Converter Forum.
I have a question regarding the ADS8354 ADC.

First, I will be using 32 clock mode for the ADC. Now, on page 37 of the datasheet there is a timing diagram (figure 90) that shows the first bit being shifted out on the falling edge of SCK clock #17, after the first 16 clocks have passed. And the last bit is shown on the 32^nd clock (since it’s 16 bit data.) However, the next page shows in Table 11 that the first bit is shifted out on the falling edge of clock #16 rather than clock #17. And it lists an empty bit on 32 rather than the last data bit as show in figure 90.

Can I get some clarification on this; they seem to be in conflict with each other.

Thank you for the help.

over 8 years ago

0 Jose Duenas over 8 years ago

TI__Genius 9975 points

Hello Ed,

Below is a zoomed in version of figure 90 of the ADS8354 datasheet.

It is important to note that the first bit is launched on the falling edge of cycle #16 of SCLK; and the bit is therefore available soon after SCLK falling edge 16. The parameter that provides such timing specification is tD_CKDO (please consult section 7.10 for its value).

Table 11 agree with figure 90, as indicated in the table, the bit is launched on the falling edge of cycle #16 of SCLK.

Hope this clarifies the working principle of the interface.

Best regards,

Jose

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ADS8354 timing diagram page 37 38