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ADS42LB69 - SNR versus Input Frequency and External Clock Jitter

Ryuji
Guru 20090 points
Other Parts Discussed in Thread: ADS42LB69

Hello,

In the datasheet of ADS42LB69 , there is the Figure 22 SNR versus Input Frequency and External Clock Jitter.
And there the 5 curves which have jitter from 35fs~200fs.

<Question 1>
Is this Figure calculated data or measured data?

<Question 2> 
Could you please let me know the integral bandwidth for this jitter ?

<Question 3>
If this data is measured data, could you please let me know the measurement structure?
And could you please let me know the method of determination for  lower limit and upper limit of bandwidth? 



Best Regards,
Ryuji Asaka

  • 0
    TI__Expert 3855 points

    Hello Ryuji,

    the curves in figure 22 are calculated, not measured. They are calculated given the formulas in the data sheet.

    Actual measurements should get pretty close to these numbers assuming:

    1. you use low phase noise signal generators to limit jitter contribution from the instruments

    2. you use bandpass filters to limit far end noise contribution from the generators

    3. you use sufficient amplitude on the clock signal to keep the ADC aperture jitter low.

    The integration bandwidth depends on your setup. On the low end you can use what is needed in your application or in measurement you can use 1/2 of the bin size of the FFT measurement. You can also check on here:

    http://www.ti.com/litv/pdf/slyt379

    In our measurements typically the lower end integration limit is 1/2 the FFT bin size and the upper end is limited by the pass band edge of the bandpass filter of the clock input.

    Tommy