I have been struggling to get a reliable front end DDR design with FIFOs that will receive data from four separate ADS62P49 ADC driven by a common PLL/clock buffer. I have implemented DDR interfaces using the supplied ADCoutput lane clocks (BUFR) with IDELAYE and IDDR elements with the individual lane clocks feeding the write side of each respective data FIFO. I have used one ADC lane clock as a common clock to drive a BUFG to act as the FIFO read side clock for all four channels.
However, despite my belief that I have plenty of setup and hold slack at the IDDR (almost 400ps at 150MHz sampling rate) I see strange problems with the FIFOs and the coherency of the data across the channels is lost.
Does TI have any reference VHDL code targeted for Xilinx that has been successfully used to test four ADS62P49 converters? My approach may be correct and my problems due to incorrect constraints but I am looking for any kind of baseline design from which I can validate my approach.
Thanks,
Craig
