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DAC38J84EVM: Why does my sync assert during ILA?

David Suh
Prodigy 60 points

Part Number: DAC38J84EVM
Other Parts Discussed in Thread: LMK04828, DAC38J84

I'm interfacing the DAC38J84EVM with a Xilinx KCU105 board. I seem to be entering code group synchronization and ILA fine, but I'm getting what looks like a resync request during ILA. As shown below, my JESD tx core re-enters code group sync and ILA a second time, and the link seems to be up after that. I do not get any alarms for the receivers I'm using either, but the waveform that I probe at the output of the DAC is not as expected. I am sending a sawtooth pattern, but the DAC output on an oscilloscope shows something different. I would like to know if this issue might be related to the sync assert that I am seeing during ILA, or any clues as to where to look would be much appreciated.

What I have checked so far:

- I have double checked the configuration parameters that are being sent over in the 2nd multiframe of ILA, and they match with what is programmed by the GUI software.

- I have tried the short test and see no errors from the alarms.

My JESD configuration is as follows:

  • 0
    TI__Guru* 91947 points

    David,

    Try setting bit 5 of registers config81 and config84 to a "0" which will not issue a re-sync if there is a link configuration error. What frequency is the reference clock you are sending to the FPGA? Can you send us the test pattern to try with our setup?  

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 60 points
    Hi Jim,

    I've tried setting both registers to 0 and I am still seeing a re-sync. The ref clock frequency I am using is the 184.32MHz FPGA clock sourced from the eval board. The test pattern is 0xF1, 0xE2 (I recall seeing this in another document referencing this DAC eval board).

    Thanks
  • 0 in reply to David Suh
    TI__Guru* 91947 points

    4421.cfgDavid,

    Here is the configuration file I used with our DAC EVM using your settings. I would try this and see if it fixes the problem.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 60 points
    Hi Jim,

    Thanks for your reply. Unfortunately, I get the same results as before using the config file. If this is the correct DAC configuration with respect to my JESD settings, would you know where I could have possibly gone wrong?

    On the FPGA side, I have my jesd tx core taking in the differential clock pair from the LMK04828 (DCLKOUT0). The differential sync to the FPGA is sourced from DAC38J84 (SYNCBP) and sysref comes from the LMK04828 (SDCLKOUT1). Line rate and ref clock frequencies for my jesd core match with those on the GUI.
  • 0 in reply to David Suh
    Prodigy 60 points
    After looking though the Xilinx JESD204 lounge project, I found out that the order of my framed data was wrong. This was fixed and all is working fine now.