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ADS1278: TDM mode sample rate limitation?

Andrew Marsh
Intellectual 765 points

Part Number: ADS1278

I am collecting data from the ADS1278 in fixed position TDM mode. My receiver is configured to latch data on the rising edge of SCLK as the ADC should be shifting on the falling edge. Running acquisitions at 144kHz I am always seeing the MSB of DOUT1 equal to one and the remaining DOUT1 bits at expected values. Data from the other 7 channels looks correct. I do have DVDD set to 2V and IOVDD at 3.3V.

After looking closer at the datasheet trying to debug this I am starting to doubt that you can actually get 8 channels at 144kHz in TDM mode. According to the frame-sync timing specification the min CLK period in high speed mode is 27ns. If you assume 50% duty cycle on the clock that gives you 13.5ns. However the allowed DOUT MSB propagation delay can be up to 21ns. Assuming 8 channels at 24 bits and a period = 2 * propagation delay, the best you can guarantee is ~93kHz.

Can anybody confirm my suspicions that this part is sample rate limited in TDM mode or am I seeing something else?

  • 0
    TI__Guru 69186 points

    Hello Andrew,

    Thanks for your post.

    You are absolutely right that the MSB propagation delay will cause you to misread the MSB at the highest data rates in the ADS1278. Specifically, you can run into this issue whenever half the SCLK period is less than tMSBPD or tDOPD, as you mentioned.

    A workaround solution is shown in Figure 88 of the datasheet (though not explicitly called out). In that figure, you'll see a D flip-flop and an inverter that can be used to re-clock the data from the ADS1278. You will still read the data on the rising edge of SCLK as seen by the MCU; however, it will be delayed by one SCLK period. Below I've included a timing diagram to help illustrate how this will work:

    Best Regards,