Hello
I have posted a question about the "Minimum integration time in continuous mode" for the DDC112 device in this thread.
I have a problem with the answer. The answer begs another question. The thread is now locked so I have to ask the question in this new post.
Question:
Maybe read the thread referred to above again. It should be quick.
The datasheet says that switch over between continuous and discontinuous mode starts at 4794 clocks on the CONV signal. Matt indicated that when the CONV signal is high/low for less than 5000 clock (500 us @ 10MHz) one should start expecting the DDC112 device to change over to the discontinuous mode. That is 5000 - 4794 = 206 clocks away from the 4794 switch over point in the datasheet.
Now my question are:
Where is the switch over point when coming from the discontinuous mode approaching the continuous mode.
Is it at 4794 - 206 = 4,588 clocks?
Or is it still at 5000 clocks.
If the answer is latter i.e. (5000 clocks) it would be silly of TI to indicate that the switch over is at 4794 clocks when it is in fact at 5000 clocks.
My guess is that switch over is in fact at 4794 but TI gives the minimum continuous integration time as 5000 clock cycles because one can have a CONV signal that might be deformed due to signal paths with buffers etc. that causes pulse width distortion = duty cycle changes. Duty cycle change will cause the CONV signal to be in a given state high/low for less than 5000 clock cycles i.e. even so much as less than 4794 clock in a given state for a VERY BAD signal path. That is then where you change over to discontinuous mode unintentionally. But if that is the case then you have a big problem. If your signal path buffer can cause a duty cycle change of 206/5000 = 4.12% you will always have an integration time that is +/- 4.12% of your intended integration time. That is a big error which should be avoided by choosing good components in your signal path or at least compensate for it to some extend in your CONV signal generation.
So I do not buy the the possible explanation given above for a minimum continuous integration time of 5000 clocks. If the limitation (minimum continuous mode integration time = 500us [5000 clocks at 10MHz]) is true there must be another reason for it other than that you switch over to discontinuous integration at this point.
My guess is that switch over is in fact at 4794 clocks for CONV in the high or low state. What one should do is choose ample margin around this switch over point say 30 clock cycles and then choose your switch over points as follows:
Cont > Dcont = 4794 + 30 = 4824 clocks
Dcont > Cont = 4793 - 30 = 4763 clocks
I use SI8620BB-B-IS digital isolators with 1.5ns pulse width distortion. That is far 1.5% distortion of 1 clock cycle at 10 MHz. So it should not be a problem. But there might be other sources.
Texas please shed some more light on this for me.
