Other Parts Discussed in Thread: REF5025, REF6225
Section 9.3.8.2 applies to an external voltage reference.
Using this external reference configuration, we are supplying a 2.5 V (approximately) signal between AIN0 and AIN1. The last paragraph in sect 9. 3.8.2 states a 100 nF, or 0.1 uF, should be placed across the input pins. Is this required?
We do have and op amp circuit directly connected to the analog pins. If the cap is placed on the output of the op amp, how is the performance impacted? Data sheet point to Fig 34.
Although the input is fairly hi Z, adding a isolating resistor between the op amp output and AINx will degrade this voltage.
Please comment on what design practices should be taken in this scenario (if removal of cap is fine, or some other design guidance.