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DAC3484EVM: CLKIN not working...

Part Number: DAC3484EVM
Other Parts Discussed in Thread: CDCE62005, , LMK04828, DAC3484

I'm driving the J9 CLKIN input with a 153.6MHz LVPECL20 output from an LMK04828B_EVM CLKout0+/-.  I've reduced the emitter resistance to 120 Ohms an have managed to get a 600mV signal riding on the 2V bias of the Primary clock input to the on-board CDCE62005 IC.  I think I need help getting this CDCE62005 chip to operate.  Upon powering up, the FPGA clock outputs to the J13 connector has a signal outputting from U3P/N outputs (i.e. Y3:FPGACLK1 on the CDCE62006 tab of the DAC3484EVM Software Control tab) so I know that the DAC3484EVM is operational and I've even run it connected to a TSW1400 and seen that work.  I'm obviously doing something wrong but I don't know what.  The CLKout0+/- is connected to an ADC-WB-BB balun.  With or without the R1/R3 resistors, I'm not getting much of a difference in signal amplitude. Attached below is my setup for both cards.  The LMK04828B_EVM is operational, but the DAC3484EVM is not seeing my clock input signal and producing the desired 131.072MHz output on U3P/N.

LMK04828-dual-loop, 10 MHz to 122.88 MHz to 3072 MHz to 153.6 MHz.txt
[SETUP]
ADDRESS=888
CLOCK=8
DATA=4
LE=2
PART=LMK04828B
IFACE=SPI
ADDRESS_I2C=0x0

[PINS]
PINNAME00=SYNC
LOCATION00=7
PINVALUE00=False
PINNAME01=CLKin0_SEL
LOCATION01=0
PINVALUE01=False
PINNAME02=RESET
LOCATION02=3
PINVALUE02=False

[MODES]
NAME00=R0 (INIT)
VALUE00=144
NAME01=R0
VALUE01=16
NAME02=R2
VALUE02=512
NAME03=R3
VALUE03=774
NAME04=R4
VALUE04=1232
NAME05=R5
VALUE05=1371
NAME06=R6
VALUE06=1536
NAME07=R12
VALUE07=3153
NAME08=R13
VALUE08=3332
NAME09=R256
VALUE09=65556
NAME10=R257
VALUE10=65877
NAME11=R258
VALUE11=66133
NAME12=R259
VALUE12=66305
NAME13=R260
VALUE13=66562
NAME14=R261
VALUE14=66816
NAME15=R262
VALUE15=67184
NAME16=R263
VALUE16=67430
NAME17=R264
VALUE17=67608
NAME18=R265
VALUE18=67925
NAME19=R266
VALUE19=68181
NAME20=R267
VALUE20=68352
NAME21=R268
VALUE21=68610
NAME22=R269
VALUE22=68864
NAME23=R270
VALUE23=69232
NAME24=R271
VALUE24=69472
NAME25=R272
VALUE25=69640
NAME26=R273
VALUE26=69973
NAME27=R274
VALUE27=70229
NAME28=R275
VALUE28=70400
NAME29=R276
VALUE29=70658
NAME30=R277
VALUE30=70912
NAME31=R278
VALUE31=71417
NAME32=R279
VALUE32=71424
NAME33=R280
VALUE33=71704
NAME34=R281
VALUE34=72021
NAME35=R282
VALUE35=72277
NAME36=R283
VALUE36=72448
NAME37=R284
VALUE37=72706
NAME38=R285
VALUE38=72960
NAME39=R286
VALUE39=73337
NAME40=R287
VALUE40=73523
NAME41=R288
VALUE41=73736
NAME42=R289
VALUE42=74069
NAME43=R290
VALUE43=74325
NAME44=R291
VALUE44=74496
NAME45=R292
VALUE45=74754
NAME46=R293
VALUE46=75008
NAME47=R294
VALUE47=75513
NAME48=R295
VALUE48=75520
NAME49=R296
VALUE49=75784
NAME50=R297
VALUE50=76117
NAME51=R298
VALUE51=76373
NAME52=R299
VALUE52=76544
NAME53=R300
VALUE53=76802
NAME54=R301
VALUE54=77056
NAME55=R302
VALUE55=77561
NAME56=R303
VALUE56=77568
NAME57=R304
VALUE57=77830
NAME58=R305
VALUE58=78165
NAME59=R306
VALUE59=78421
NAME60=R307
VALUE60=78592
NAME61=R308
VALUE61=78850
NAME62=R309
VALUE62=79104
NAME63=R310
VALUE63=79481
NAME64=R311
VALUE64=79667
NAME65=R312
VALUE65=79904
NAME66=R313
VALUE66=80128
NAME67=R314
VALUE67=80396
NAME68=R315
VALUE68=80640
NAME69=R316
VALUE69=80896
NAME70=R317
VALUE70=81160
NAME71=R318
VALUE71=81411
NAME72=R319
VALUE72=81664
NAME73=R320
VALUE73=81933
NAME74=R321
VALUE74=82176
NAME75=R322
VALUE75=82432
NAME76=R323
VALUE76=82705
NAME77=R324
VALUE77=83147
NAME78=R325
VALUE78=83327
NAME79=R326
VALUE79=83480
NAME80=R327
VALUE80=83738
NAME81=R328
VALUE81=83970
NAME82=R329
VALUE82=84290
NAME83=R330
VALUE83=84482
NAME84=R331
VALUE84=84758
NAME85=R332
VALUE85=84992
NAME86=R333
VALUE86=85248
NAME87=R334
VALUE87=85696
NAME88=R335
VALUE88=85887
NAME89=R336
VALUE89=86019
NAME90=R337
VALUE90=86274
NAME91=R338
VALUE91=86528
NAME92=R339
VALUE92=86784
NAME93=R340
VALUE93=87160
NAME94=R341
VALUE94=87296
NAME95=R342
VALUE95=87677
NAME96=R343
VALUE96=87808
NAME97=R344
VALUE97=88214
NAME98=R345
VALUE98=88326
NAME99=R346
VALUE99=88576
NAME100=R347
VALUE100=89044
NAME101=R348
VALUE101=89120
NAME102=R349
VALUE102=89344
NAME103=R350
VALUE103=89600
NAME104=R351
VALUE104=89867
NAME105=R352
VALUE105=90112
NAME106=R353
VALUE106=90369
NAME107=R354
VALUE107=90788
NAME108=R355
VALUE108=90880
NAME109=R356
VALUE109=91136
NAME110=R357
VALUE110=91404
NAME111=R369
VALUE111=94634
NAME112=R370
VALUE112=94722
NAME113=R380
VALUE113=97301
NAME114=R381
VALUE114=97587
NAME115=R358
VALUE115=91648
NAME116=R359
VALUE116=91904
NAME117=R360
VALUE117=92165
NAME118=R361
VALUE118=92505
NAME119=R362
VALUE119=92704
NAME120=R363
VALUE120=92928
NAME121=R364
VALUE121=93184
NAME122=R365
VALUE122=93440
NAME123=R366
VALUE123=93715
NAME124=R371
VALUE124=94976
NAME125=R8189
VALUE125=2096384
NAME126=R8190
VALUE126=2096640
NAME127=R8191
VALUE127=2096979

[FLEX]
bSetFeedback_CLKin1=CLKin1 (External)
bSetFeedback_DCLKout6=DCLKout6
bSetFeedback_DCLKout8=DCLKout8
bSetFeedback_SYSREFDIV=SYSREF divider
bSetJESD204B_Continuous=Continuous
bSetJESD204B_NoJESD204B_withoutSYSREFDivider=No JESD204B
bSetJESD204B_Pulser=Pulser
bSetJESD204B_Reclocked=Reclocked
bSetJESD204B_SYSREFREQ=SYSREF Request
bSetMode_Distribution=Set Distribution
bSetMode_DualLoop=Set Dual Loop
bSetMode_DualLoop0DelayCascaded=Set Dual Loop 0-Delay Cascaded
bSetMode_DualLoop0DelayNested=Set Dual Loop 0-Delay Nested
bSetMode_SingleLoop=Set Single Loop
bSetMode_SingleLoop0Delay=Set Single Loop 0-Delay
bSet_CLKin0toOff=CLKin0 Off
bSet_CLKin0toPLL1=CLKin0 drives PLL1
bSet_CLKin0toSYSREF=CLKin0 drives SYNC/SYSREF
bSet_CLKin0toSYSREF_Direct=CLKin0 drives SYNC/SYSREF direct
bSet_CLKin1_ExternalVCO=CLKin1 drives Clock Distribution (external VCO/distribution mode)
bSet_CLKin1toOff=CLKin1 Off
bSet_CLKin1toPLL1=CLKin1 drives PLL1
bSet_CLKin2_Input=CLKin2 for PLL1
CLKDIST_FREQ=3072
CLKin0_FREQ=122.88
CLKin1_FREQ=10
CLKin2_FREQ=153.6
CLKin_SEL_AUTOPINSMODE=1
EXT_VCXO_FREQ=122.88
FB_MUX_FREQ=128
FB_MUX_FREQ_MHz=
OSC_FREQ=122.88
OSCin_SOURCE=0
PLL1_PD_FREQ=0.08
PLL2_PD_FREQ=122.88
PLL_FBMUX_WARNING_TEXT=
PLL_WARNING_TEXT=
WARNING_TEXT_PLL1=
WARNING_TEXT_PLL2=
CLKDIST_FREQ=3072
SYSREF_FREQ=1
bSYNC_DIS_AllOff=All Off
bSYNC_DIS_AllOn=All On
bSYNC_DIS_CLKOff=DC Off
bSYNC_DIS_CLKOn=DC On
bSYNC_Dividers=SYNC Dividers
bSendPulsesViaSPI=Send Pulses
bSetJESD204B_Continuous=Continuous
bSetJESD204B_Pulser=Pulser
bSetJESD204B_RX_CLKin0=CLKin0
bSetJESD204B_RX_CLKin0_Bypass=CLKin0 Bypass
bSetJESD204B_RX_Ignore=None
bSetJESD204B_RX_Reclocked=Re-Clocked
bSetJESD204B_RX_SYNCpin=SYNC Pin
bSetJESD204B_SYSREFREQ=SYSREF Request
bSetSYNC_Normal=Normal
stSYSREF_CLR_WARNING=
CLKDIST_FREQ=3072
CLKout0_FREQ=153.6
CLKout10_FREQ=384
CLKout11_FREQ=384
CLKout12_FREQ=512
CLKout13_FREQ=512
CLKout1_FREQ=153.6
CLKout2_FREQ=128
CLKout3_FREQ=128
CLKout4_FREQ=384
CLKout5_FREQ=384
CLKout6_FREQ=128
CLKout7_FREQ=128
CLKout8_FREQ=384
CLKout9_FREQ=384
OSCout_FREQ=122.88
SDCLKout11_TEXT=
SDCLKout13_TEXT=
SDCLKout1_TEXT=
SDCLKout3_TEXT=
SDCLKout5_TEXT=
SDCLKout7_TEXT=
SDCLKout9_TEXT=
SYSREF_FREQ=1

DAC3484EVM_setup_registers.txt
   x00	   x0080
   x01	   x0100
   x02	   x8002
   x03	   x0001
   x04	   x4068
   x05	   x0260
   x06	   x2400
   x07	   x0000
   x08	   x0000
   x09	   x8000
   x0A	   x0000
   x0B	   x0000
   x0C	   x0000
   x0D	   x0000
   x0E	   x0000
   x0F	   x0000
   x10	   x0000
   x11	   x0000
   x12	   x0000
   x13	   x0000
   x14	   x0000
   x15	   x0000
   x16	   x0000
   x17	   x0000
   x18	   x0007
   x19	   x0000
   x1A	   x0020
   x1B	   x0000
   x1C	   x0007
   x1D	   x0054
   x1E	   x0000
   x1F	   x0002
   x20	   x2400
   x22	   x1B1B
   x23	   x0000
   x24	   x0000
   x25	   x0000
   x26	   x0000
   x27	   x0000
   x28	   x0000
   x29	   x0000
   x2A	   x0000
   x2B	   x0000
   x2C	   x0000
   x2D	   x0000
   x2E	   x0000
   x2F	   x0000
   x30	   x0000
   x7F	   x0004
CDCE62005 Registers
Freq:0.000000MHz
Address	Data
00		00400020
01		80040001
02		81800002
03		81040003
04		00040004
05		01280A55
06		04BE3F76
07		170037F7
08		20001C08

  • Hello Ron,

    I recommend to first try to inject the J9 CLKIN clock source from an external test equipment to see if the connection to the J9 and also the J9 connector is properly soldered down to the EVM. There may be cases where the SMA connector center pin may not be making proper contact due to mechanical stress. Try to increase the J9 CLKIN power higher as described in the EVM user's guide to see if you can improve the situation. Perhaps you may touch up the soldering with soldering iron. If necessary, please contact your EVM supplier for an EVM replacement.

    You may also run the default setup script within the DAC3484 EVM GUI, which are known good test setup to eliminate variables of the clock chip configuration. The default scripts have setup for 1228.8MSPS of DAC and also 983.04MSPS of DAC with the CDCE62005 in clock distribution mode. If you want to set the CDCE62005 in PLL mode, we also have some configurations as well.

    For more advanced configuration of the CDCE62005 outside of the scope of the default EVM setup, we may have to refer you to the clocking forum for more assistance. They have more expertise in helping the advanced setup.
    -Kang
  • So it doesn't matter if I try to run the CDCE62005 with a signal generator with 1.5Vrms input signal like the examples say to do in the DAC3484EVM document.  I get no output on Y2 and Y3 (set to 524.288MHz FDAC and 131.072MHz FPGACLK1).  I'm just seeing a 2.7VDC level on both the CDC_IO1 and CDC_IO1\ outputs

    Here's the setup that I tried:

    DAC3484EVM_setup_registers_19_2MHz_input_131_072MHz_FPGACLK1_Y3.txt
       x00	   x0000
       x01	   x0100
       x02	   x0000
       x03	   x0000
       x04	   x4028
       x05	   x0220
       x06	   x2F00
       x07	   x0000
       x08	   x0000
       x09	   x0000
       x0A	   x0000
       x0B	   x0000
       x0C	   x0000
       x0D	   x0000
       x0E	   x0000
       x0F	   x0000
       x10	   x0000
       x11	   x0000
       x12	   x0000
       x13	   x0000
       x14	   x0000
       x15	   x0000
       x16	   x0000
       x17	   x0000
       x18	   x0007
       x19	   x0000
       x1A	   x0020
       x1B	   x0000
       x1C	   x0007
       x1D	   x0054
       x1E	   x0000
       x1F	   x0000
       x20	   x0000
       x22	   x0000
       x23	   x0000
       x24	   x0000
       x25	   x0000
       x26	   x0000
       x27	   x0000
       x28	   x0000
       x29	   x0000
       x2A	   x0000
       x2B	   x0000
       x2C	   x0000
       x2D	   x0000
       x2E	   x0000
       x2F	   x0000
       x30	   x0000
       x7F	   x0004
    CDCE62005 Registers
    Freq:0.000000MHz
    Address	Data
    00		00400020
    01		80040001
    02		81800002
    03		81040003
    04		00040004
    05		01280A55
    06		04B43F76
    07		170037F7
    08		20001C08

  • Ron,

    I am referring to the following:
    C:\Program Files (x86)\Texas Instruments\DAC348x\EVM Configuration File Released

    If you want us to try your setup, you have to be more specific on your application and each settings from the clock chain to the DAC setup.
    I am look for a diagram that describes what you are doing (i.e. clock rate, interpolation, NCOs, etc)
  • The setup linked above is a setup that receives a 19.2MHz on Pri_REF+, 1.5Vpk sinewave and produces a 131.072MHz LVDS signal on Y3 and a 524.288MHz LVDS signal on Y2. I tried this setup as I have a 0-30MHz signal generator in my test avaliable equipment . This was in response to signal levels being too low for the DAC3484EVM CLKIN on J9 that was originally 153.6MHz LVPECL20 CLKout0 from a LMK04828B_EVM module which is my end goal. I'm trying to send a 131.072MHz LVDS clock out the FPGA_CLKOUT lines over the FMC connector and use the 524.288MHz for a 16x interpolation clock to the DAC.

    My end goal is a reference input clock of 153.6MHz (LMK04828B_EVM CLKOUT0 output, referenced to a 10MHz input clock) and an FPGA_CLKOUTP/N of 131.072MHz and a DACCLK of 524.288MHz (i.e. for a 16x interpolation).  Attached below is the DAC3484EVM setup for the 153.6MHz input.

    DAC3484EVM_setup_registers_153_6MHz_in_524_288MHz_DACCLK_for_16x.txt
       x00	   x0880
       x01	   x0100
       x02	   x8002
       x03	   x0001
       x04	   x4068
       x05	   x0260
       x06	   x2500
       x07	   x0000
       x08	   x0000
       x09	   x8000
       x0A	   x0000
       x0B	   x0000
       x0C	   x0000
       x0D	   x0000
       x0E	   x0000
       x0F	   x0000
       x10	   x0000
       x11	   x0000
       x12	   x0000
       x13	   x0000
       x14	   x0000
       x15	   x0000
       x16	   x0000
       x17	   x0000
       x18	   x0007
       x19	   x0000
       x1A	   x0020
       x1B	   x0000
       x1C	   x0007
       x1D	   x0054
       x1E	   x0000
       x1F	   x0002
       x20	   x2400
       x22	   x1B1B
       x23	   x0000
       x24	   x0000
       x25	   x0000
       x26	   x0000
       x27	   x0000
       x28	   x0000
       x29	   x0000
       x2A	   x0000
       x2B	   x0000
       x2C	   x0000
       x2D	   x0000
       x2E	   x0000
       x2F	   x0000
       x30	   x0000
       x7F	   x0004
    CDCE62005 Registers
    Freq:0.000000MHz
    Address	Data
    00		00400020
    01		80040001
    02		81800002
    03		81040003
    04		00040004
    05		01280A55
    06		04BE3F76
    07		170037F7
    08		20001C08

  • Hi Ron,

    I will have to take a look at the EVM and get back to you. Hopefully by the end of next week.

    -Kang

  • I received some help from Rob Rodrigues and was able to get the 131.072MHz output to the FPGA_CLKOUT signals but the 530.2255MHz outputs to the DACCLK appear to be really low signal levels according to the spectrum analyzer and more like 524.294MHz around -68dB signal strength.  I need a fast oscope to look at the signal, but right now I have the RSA306 Spectrum Analyzer.  linked is my setup for this card.

    4857.DAC3484EVM_setup_registers_153_6MHz_in_524_288MHz_DACCLK_for_16x.txt
       x00	   x0800
       x01	   x0100
       x02	   x8002
       x03	   x0001
       x04	   x4068
       x05	   x0260
       x06	   x2700
       x07	   x0000
       x08	   x0000
       x09	   x8000
       x0A	   x0000
       x0B	   x0000
       x0C	   x0000
       x0D	   x0000
       x0E	   x0000
       x0F	   x0000
       x10	   x0000
       x11	   x0000
       x12	   x0000
       x13	   x0000
       x14	   x0000
       x15	   x0000
       x16	   x0000
       x17	   x0000
       x18	   x0007
       x19	   x0000
       x1A	   x0020
       x1B	   x0000
       x1C	   x0007
       x1D	   x0054
       x1E	   x0000
       x1F	   x0002
       x20	   x2400
       x22	   x1B1B
       x23	   x0000
       x24	   x0000
       x25	   x0000
       x26	   x0000
       x27	   x0000
       x28	   x0000
       x29	   x0000
       x2A	   x0000
       x2B	   x0000
       x2C	   x0000
       x2D	   x0000
       x2E	   x0000
       x2F	   x0000
       x30	   x0000
       x7F	   x0004
    CDCE62005 Registers
    Freq:153.6MHz
    Address	Data
    00		68040320
    01		68800301
    02		81800302
    03		EB040303
    04		68860314
    05		11280BE5
    06		440F3F76
    07		BDF8FBC7
    08		20009D98

  • Ron,

    with your latest setup file, I can observe the 524.294MHz clock (LVPECL swing) at 2Vpp measured on C3 and C4 for the DACCLK. Also, I was measuring 2Vpp FPGA clock at 2Vpp as well. The measurement was done with Tektronics TDS5104B scope with P6248 diff probe.

    The amplitude seems correct with the CDCE62005 locked. If you need to tune the frequency, you will have to work offline with the clock team on this. I will close this post for now.

    -Kang