DAC3482EVM: FIFO Collisions in DAC3482EVM Setup Example

Hi Chris,

I recommend that you check all the clocks on the FPGA and also the OSTR are set correctly. If these synchronization clocks are set incorrectly, the FIFO input/output rate will have mismatch and cause collision.

You are using the DAC3482 EVM with DAC3484 configuration. I also suggest that you use the proper configuration file for the DAC3482. The interface rate between the two different DACs are different and may cause FIFO error also (and also the entire setup may not be correct).

-Kang

Hi Kang,

Thanks for your response. I had a typo in my first post, the file that I am using to load the register values is actually "DAC3482_FDAC_1228p8MHz_4xint_NCO_30MHz_QMCon.txt" - sorry for confusing matters.

So I did go back and reconfirm the clock frequencies. Specifically:

(1) probed R68 to confirm the frequency of my external source is preserved through the CDCE62005 such that DACCLK is 1228.8 MHz.

(2) probed R62 to confirm that the FIFO-OSTR clock is running at Fdac/64 (i.e. 19.2 MHz). I'm assuming Fdac/64 is correct as the aforementioned register file I am loading for the DAC3482 register values controls this. This seems consistent with the OSTR division I have seen for the DAC3482EVM in other PPTs I have seen posted in this forum.

(3) probed R116 to confirm FPGA Clock 1 is running at Fdac/4/4 (i.e. 76.8 MHz).

Unless I am missing something, these clock frequencies are consistent with what is prescribed in the manual that you referenced.

In HSPro, I generate a single 10 MHz complex tone at 307.2 MSps (Fdac/4[interpolation]) as prescribed by the setup procedure in the manual; maybe this isn't correct for the DAC3482? When I do this, I observe that DATACLK (as probed on SJP11) is running at 307.2 MHz. Can you confirm this is the correct frequency for DATACLK in this use case with the dac3482evm? The frequency of DATACLK also appears to be invariant to the sample rate specified in HSPro so I guess DATACLK is hard-coded in the firmware and is not controlled by the GUI at all - is this correct?

I should also point out that the voltage levels for the respective logic signals all appear to be consistent with the corresponding standard. Is there any further explanation as to why I am still observing FIFO collisions?

-Chris

Hi Chris,

I believe your DAC3482EVM is configured correctly as the default script has been thoroughly verified against the TSW1400. With the TSW1406, it is possible that you will have to keep decreasing the DACCLK rate so the overall LVDS IO rate can be dropped. I have a feeling that the TSW1406, being a low cost solution, simply can't keep up the I/O rate of the DAC3482 with 307.2MSPS (614.4MBPS LVDS rate). The IO rate for the TSW1406 is limited by 1GBPS, but I am not sure how this number was derived. I know that there was a rate limitation during the design of the TSW1406. Perhaps you can lower the overall clock rate to 614.4MHz at the DACCLK with the data rate at 153.6MSPS to try again.

The designer for the TSW1406 EVM is no longer with TI. There is simply not a whole lot of support left for the TSW1406. I recommend that if you have a TSW1400 available, please give it a try as well.

-Kang

Hi Kang,

                I lowered DACCLK to 128 MHz (too low?) so that DATACLK is now running at 32 MHz. The GUI is still reporting FIFO collisions when I enable those alarms and the spectrum still appears erradic. Should DATACLK be running at DACCLK/4 for this example setup? If so, is there anything else I can do to understand why the collisions continue to occur? I'm wondering if I have a setup issue or a malfunctioning board.

Chris

Hi Chris,
sorry, in the short term I am running out of ideas. I am more familiar with the TSW1400 than the TSW1406. The best approach is for me to duplicate it on the TSW1406. However, I am running a bit low on bandwidth due to various projects. I will have to see if I can spend some time late next week to work this in.
-Kang