ADC3244EVM: ADC sample data seems weird

Hi Yahwen,

My first suggestion is to disable the chopper if you are testing a constant input. This can be done by writing  0x02 to registers 0x422 and 0x522 .

Additionally, I would consider using the digital test patterns to help validate the ADC / FPGA interface. This will take the analog portion out of the mix so that you can just focus on the LVDS interface.

I am not certain as to why the FCLK is misbehaving below 50 MHz. I will investigate this further, and get back with you.

Best Regards,

Dan

Hi Dan,

Thanks for your quick response, I will try your suggestion and see if it could help. 

Best,

Yawen

Hi Dan,

Thanks for your advice. I followed your suggestions:

1. Disable the chopper.      -->  It solves the "data with full FCLK cycle" problem, I can see the data does come with a period same as half of FCLK.

2. Take the Test Pattern.    --> It works. I can see the right waveform from DA0/DA1/DB0/DB1, and my FPGA logic can correctly decode it, which matches the pattern that I sent through the GUI.    (My ADC->FPGA link should be great)

But,

a. The low-frequency CLKIN problem still exists. 

b. Once I choose the normal operation (not test pattern), the ADC sample outputs will be odd, like one channel always next to 0x3FFF, one channel always close to 0x0000, no matter what signals I sent to the Analog Input.

c. Seems the ADC FCLK and DCLK do not function well, even for CLKIN over 50MHz cases. Although from the Xilinx Internal Logic Analyzer, it looks good, the data could be wrong. Like in the test pattern, normally I can get correct signals from ADC, but there always some glitches/wrong data for a very short of time (maybe one or two clocks).

I'm thinking either I didn't configure the correct parameters for normal operations or ADC EVM hardware itself is the problem. I'm attaching my configurations for normal operation as follows:

• ADC3244 EVM kit keeps it the way it shipped without changing any jumpers.
• The SPI register configurations remain as default: two-wire; no bit filps; bits 0,1,2,3~6 on lane 0 and 7~13 on lane 1;
• And the GUI settings are captured below:

Would the LVDS swing value make a difference? Am I missing anything? Thanks for your time!

Best,

Yawen

Hi Yawen,

With no additional ADC configuration, I have taken oscope shots of FCLK and DCLK at 100 MSPS and 25 MSPS, but I do not see degradation of the FCLK or DCLK at the output pins of the ADC. I will attempt to share these images soon.

Can you please verify that the FCLK and DCLK signals are as expected at the ADC output pins?

Additionally, I am able to capture FFT data fine at both 100 MSPS and 25 MSPS with the TSW1400EVM.

Best Regards,

Dan

Hi Dan,

Sorry for the late reply and really appreciate your time spending on my case!

I did check the FCLK signal at the ADC output pin and get the oscilloscope waveform captured below. When CLKIN frequency increase, I can observe similar results but less obvious(the degradation is smaller comparatively). 

I respect your testing results, and that should be the expected one according to the datasheet. For my case, I believe the ADC EVM I bought is somehow not functioning properly, will see what happens if I try another hardware. Again, thanks for your response!

Best,

Yawen