Other Parts Discussed in Thread: LMK04828,
Dear Supporters,
Our application is a custom integration of FMC144 with Arria A10 SoC Development Kit. There is no reference design.
We have implemented a rudimentary JESD receiver communicating with the pair of ADC16DX370s.
The 2 ADC16DX370 chips on FMC144 are configured with the default register settings. CLKIN is generated by LMK04828 at 148.5MHz.
In this bring-up test configuration, FMC144 input A2 (VINA on the 2nd ADC16DX370) is driven by a 3.3V CMOS square wave at 14.85MHz.
This SignalTap capture shows the expected behavior immediately following completion of the ILAS:
However, even though SYNCb remains high, ADC16DX370 behaves as though the link has broken around sample 930, repeatedly sending BCBC followed by foreshortened ILAS:
The link eventually is re-established, for example after sample 7936:
Unfortunately, the link breaks intermittently thereafter. Here is the final example from this SignalTap capture (after which the link remains stable for more than 2000 samples, to the end of the capture):
My questions about this behavior are
Q1: Why would ADC16DX370 behave as though the link has broken under these circumstances?
Q2: Will the link remain stable after some point, so long as SYNCb remains unasserted by the receiver?
I have further questions about the assertion of the datak bit, which identifies a byte as a control character.
This capture highlights the character FC sent during ILAS is correctly identified as a data byte:
However, this capture highlights bytes received by the FPGA which should be data bytes but for which datak happens to be asserted:
Q3: Is this the expected behavior of the datak bit?
Q4: Can the JESD receiver safely ignore the datak bit?
Hopeful thanks in advance for your answers --todd