In our application we programm the ADC via SPI before the CLKin is applied. The CLKin can only be applied for a certain time until the acqusition is done.
Once the CLKin is applied it will take some time until the PLL for DCLK/FCLK is locked - this is typically ~500us (as we measured until a stable FCLK output is present).
But it needs much more time until valid output-data are available - even if testpattern (ramp or sine) are generated internally, it takes a longer time until the testpattern data are coming at the output.
I can't say how long it takes, but after ~2 seconds the output data are stable - but this is too much for our application.
I did not find any number in the datasheet for the delay between first CLKin edge and valid-data output.
Can you please let us know if the above described behaviour is expected and what the minimum time delay between CLKin and valid-data output is ?