• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 46 subscribers
  • Views 316 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1255: Data converters forum

Martin Velek
Prodigy 80 points
Part Number: ADS1255
Other Parts Discussed in Thread: ADS1256,

Hello,

I would like to measure conversion time and compare it with the t18. The SPI master sends:

  • SYNC command
  • Wait t11
  • WAKEUP command

fCLKIN = 7.68MHz.

The settling time is measured starting at the WAKEUP is sent event and ends when DRDY/ goes low. Unfortunately, measurement via DRDY/ low-high-low is not possible because sometimes the SYNC and WAKEUP are sent during already running conversion and DRDY/ does not go low. 

According to the datasheet the "synchronization occurs on the first rising edge of the master clock after the first SCLK used to shift in the WAKEUP command.". The term synchronization is not explained further in this case with respect to the DRDY/ line. For SYNC/PDWN/ line is clearly specified when the DRDY/ goes low or high and when the conversion is started. This information is missing for the SYNC command.

What I have observed, there is always a delay of ~2.5 us between first SPI clock of the WAKEUP command and DRDY/ low-high transition. This number was measured together with several SPI speeds. However I could not find any datasheet value which would be close to it. 

Can be the total conversion time considered as t18 + 2.5us?

Best regards

Martin Velek

 

  • 0
    TI__Mastermind 35141 points

    Hi Martin,

    Do you have a scope capture to show the timing you are seeing?

    Are you using your own system or the ADS1256 PDK?

    What is your SCLK frequency?

    The answers to these questions will help to confirm / deny what you are seeing.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 80 points

    Hi Bryan,

    yes, see below. I am using ADS1256EVM rev C. only, not the PDK. The SPI + diagnostic and control signals goes to STM Discovery board with STM32F207. SYNC_PWD/ is tied to VDD, analog and digital grounds are connected together, reset signal is controlled from nucleo board. The 1.8 V is not used and rest is default. 

    Initial configuration:

    0x02U, // STATUS register, MSB output, auto calibration disabled, Buffer enabled
    0x01U, // MUX register, AIN0 positive input, AIN1 negative
    0x02U, // ADCON register, Clock Out OFF, Sensor Detect OFF, PGA = 4
    0x63, // DRATE, not filled, depends on parameterization
    0x00U, // I/O: all pins output, to prevent excess power dissipation.

    The times are not precise, I would have to use better equipment, current sampling rate is 50 MHz. The delay is always ~2.5 us. I wonder if this delay is somehow constant. 

    SPI at 1.5 MBit/s

    SPI at 390 KBit/s

  • 0 in reply to Martin Velek
    TI__Mastermind 35141 points

    Hi Martin,

    I assume this issue is independent of data rate as well, correct? So whether you are sampling at 50SPS or 30000 SPS, the delay is always 2.5 us?

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 80 points

    Hi,

    my target SPSs will be 50, 60 and 1000. All SPSs with the same behavior.

    When I was trying to reproduce it for a different SPS, I was curious about the self-calibration (0xF0) and the delay between last SPI clock high - low transition and first low - high transition on DRDY/. There is another "magic" number - ~3.3 us.

    I would expect these numbers to be placed somewhere in datasheet. I believe it does not depend on the mood of ADS1255/6/7 but the timing is deterministic.

    Best

    Martin 

  • 0 in reply to Martin Velek
    TI__Mastermind 35141 points

    Hi Martin,

    Thanks for the additional feedback.

    It sounds like the ultimate goal here is to avoid using the DRDY pin to signal when a conversion is complete, as well as understand how this correlates with the t18 timing. If you are not going to use DRDY to signal a complete conversion, then you should consider the settling time (t18) starts when the WAKEUP command completes. In your first image where SCLK = 1.5MHz, this would have provided sufficient time for the conversion to complete, since DRDY went high about midway through the WAKEUP command.

    We would recommend using DRDY to determine when a conversion completes and is ready to sent to your MCU. But this method of waiting t18 ms starting from the end of the WAKEUP command should work as well if there is a reason not to use DRDY in your system.

    -Bryan